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Part Number: TAS5756M
GVDD_REG power supply specification is not described in datasheet.
Waveform for startup sequence is attached below;
・On startup to 10 sec: 5.4V output and the after is 6.8V output.
・After I2C communication(Reset), GVDD is dropped to 5.4V for 1 sec and after become 6.8V.
Please let me know about two points question below;
①Is above waveform correct operation?
②Please let me know timing for read Vspk_GAIN/FREQ's DC voltage.
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In reply to Shawn Zheng:
In reply to Andy Liu SH:
I attached I2C command data, please see below.
In reply to Satoshi:
Let me explain why you would see the transition from 5.4V to 6.8V (See what is highlighted below).
After the TAS5756M is powered on, the GVDD_REG voltage will be around 5.4V if NO I2S clocks are provided. In addition, its voltage will be close to 7V when the TAS5756M is fed with I2S clocks and data.
The transition from 5.4V to 6.8V in your scope capture is because the I2S clocks in the customer systems are starting to run at that time.
The second transition from 6.8V to 5.4V is due to the following i2c command. Basically, the GVDD_REG voltage drops down to around 5.4V when it goes to the standby mode.
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