TAS5825M: Verilog/SystemVerilog Simulation Model

"No, I am looking for a simulation model in Verilog, VHDL or SystemVerilog to check configuration behaviour when talking to the chip using an FPGA. Many manufacturers offer such a model for their chips."

I'm on a crusade to get vendors of mixed-signal parts (ADCs, DACs, digital pots, whatnot) to provide bus-functional VHDL and Verilog simulation models for their devices. It's really not all that difficult, but it's time-consuming and the whole idea is that we'd like to verify our FPGA designs against what the vendor thinks their parts should do, not what we (as the FPGA designers) think they should do.

The usual response is, "we can send you the IBIS model" and then you have to explain how and why IBIS and VHDL are different.

Come on, TI, do better.

Dear Andy,

you are absolutely right! I will join this crusade immediately :)

As an Example why in this case it would be important to have a model:

There is a CRC calculation provided at Register 0x7E (Page 0).Now its not that simple, cuz page and book changes do not contribute to the CRC. Only Write are evaluated etc. In the DSP image itself there are some weird register writes to the CRC registers, which are undocumented. It doesn't say if this CRC is for the book, the page or the whole device. So it would be nice to have a sim model that does it exactly the same as the original chip so I don't have to guess how its gonna be in the real design. Especially cuz this will be the quick measure to figure out if the image was correctly transmitted. Reading back the device will take around 500 - 1000 ms and this will be done every once in a while, but the user doesn't want to wait a whole second for the device to start.

Best regards,

Martin