PCM1863: Maximum word length for 192kHz sample rate

Hi Anthony,

I will have to run some tests on the EVM to clearly answer your first question regarding the 192kHz/32-bit word length question.

Regarding the BCK duration (MIN) value, it appears it is a DS error and will definitely investigate and correct the same for future revision of the DS. I'll provide you the right value for the same.

Thanks.

Best regards,
Ravi

Hi Ravi,

Thanks for this. As an additional note, I find that the PLL_Lock bit in page 0 register 28 never sets after enabling the PLL. I find I can just poll the register until the PLL_Enable bit reads as set and this seems to work ok, but I wonder if the absence of this bit setting is a result of some configuration error?

For reference, I'm using the PCM1863EVM board with the PCM9211 IC removed and the I2C lines cut before they get to J7 so I can configure the device via SPI and the included oscillator Y0 is installed. I also use the below register configuration - I've included basic prototypes for my read and write functions so you can see which value is which:

void SPI_PCM186x_write(unsigned int RegNum, unsigned int RegVal, unsigned int block_until_done);
unsigned int SPI_PCM186x_read(unsigned int RegNum);

void PCM1863_setup(void)
{
    unsigned int SPI_debug;

    SPI_PCM186x_write(0x00, 0xFE, 1);       // Reset the codec

    delay_inst(20000);                      // Wait some time for reset to happen

    SPI_PCM186x_write(0x00, 0x00, 1);       // Select page 0
    SPI_PCM186x_write(0x01, 0x00, 1);       // Set default Ch1_L Gain
    SPI_PCM186x_write(0x02, 0x00, 1);       // Set default Ch1_R Gain
    SPI_PCM186x_write(0x05, 0x86, 1);       // Set gain behaviour - Smooth changes, Independent PGA control across channels, auto clip suppression off
    SPI_PCM186x_write(0x06, 0x41, 1);       // Configure ADC1 Input_L - VinL1[SE] = 0x41 - Vin1P-Vin1M[DIFF] = 0x50
    SPI_PCM186x_write(0x07, 0x42, 1);       // Configure ADC1 Input_L - VinR2[SE] = 0x42 - Vin2P-Vin2M[DIFF] = 0x50

    SPI_PCM186x_write(0x0B, 0x00, 1);       // Configure serial audio format - RX stuff - don't care, 32-bit word, I2S format

    SPI_PCM186x_write(0x19, 0x00, 1);       // Make sure auto gain-mapping is enabled

    // Clocking configuration

        // Configure clock source and dividers for ADC/DSP1/DSP2 cores
        SPI_PCM186x_write(0x20, 0xB6, 1);       // Configure clocking - Xtal as clock source, Master mode and PLL as clock source for all except ADC on SCK
        SPI_PCM186x_write(0x21, 0x01, 1);       // Halve PLL output of 98.304 MHz for DSP1 to generate requisite 49.152 MHz clock (div. by (N+1))
        SPI_PCM186x_write(0x22, 0x01, 1);       // Halve PLL output of 98.304 MHz for DSP2 to generate requisite 49.152 MHz clock (div. by (N+1))
        SPI_PCM186x_write(0x23, 0x03, 1);       // Divide SCK/PLL (as selected above) by 4 to generate ADC clock of 6.144 MHz (div. by (N+1))

        // Configure bit clock and sample clock generation
        SPI_PCM186x_write(0x25, 0x03, 1);       // Divide PLL output by 4 to generate SCK output of 24.576 MHz (div. by (N+1))
        SPI_PCM186x_write(0x26, 0x01, 1);       // Divide SCK output by 2 to generate BCK of 12.288 MHz (div. by (N+1))
        SPI_PCM186x_write(0x27, 0x3F, 1);       // Divide BCK output by 64 to generate LRCK of 192 kHz (div. by (N+1))

        // Configure PLL to output 98.304 MHz (output must be within 64-100MHz) - PLLOUT = IN * K*R/P, K = J.D (J integer part, D decimal part)
        SPI_PCM186x_write(0x28, 0x00, 1);       // Disable PLL and set SCK as input
        SPI_PCM186x_write(0x29, 0x03, 1);       // Set P = 4 (1/(N+1)) for PLL divide
        SPI_PCM186x_write(0x2A, 0x01, 1);       // Set R = 2 (*(N+1)) for PLL multiply
        SPI_PCM186x_write(0x2B, 0x08, 1);       // Set J = 8 (*N) for PLL multiply (K = J.D)
        SPI_PCM186x_write(0x2C, 0x00, 1);       // Set D = 0 (LSB)
        SPI_PCM186x_write(0x2D, 0x00, 1);       // Set D = 0 (MSB)
        SPI_PCM186x_write(0x28, 0x01, 1);       // Enable PLL and set SCK as input

        SPI_debug = 0;

        while( (SPI_debug & 0x01) == 0 )   // Wait for PLL_Enable bit to read as set
        {
            delay_inst(2000);
            SPI_debug = SPI_PCM186x_read(0x28);
        }

    SPI_PCM186x_write(0x11, 0x00, 1);       // Set GPIO3 as GPIO
    SPI_PCM186x_write(0x13, 0x40, 1);       // Set GPIO3 as O/P
    SPI_PCM186x_write(0x14, 0x80, 1);       // Set GPIO 3 as high to enable LED to show as done
}

Hi Anthony,

you are correct...if the PLL configuration is not correct, it can result in PLL_LOCK bit not set which is also reflected in poor performance measure on the output signal. In addition, we have register which are indicating any clock errors as reported by CLK_ERR_STAT (Page.0 0x72) which also is useful to keep track of the right setting.

I'll review the settings in detail and will give you feedback. I think the comments are pretty clear but in case I need additional clarifications on your overall settings for your application, I'll ping you back tmrw. Thanks.

Best regards,
Ravi

Hi Ravi,

Have you been able to investigate the matter above. Whilst I can proceed on what I have so far, my worry is that down the line the fact that the PLL is never showing that it is locked may cause problems with jitter/wandering sample rate down the line which may stop my project from working.

If it helps, I'm interfacing this board with a TMS320C5535 platform, although I think with the abstracted code the problem can be isolated to the ADC itself.

Many thanks.

Antony

Hi Antony,
I do plan to review the config and test the same on my end on EVM. Ideally the PLL lock bit should be set but I have had some instances where the lock bit does not asserted inspite of the PLL configuration being accurate. I'll have an update once I have the testing completed on my end. Thanks.

Best regards,
Ravi