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Part Number: TLV320AIC3254
Can you provide more information about the miniDSP_D_Cycles and miniDSP_A_Cycles in the TLV320AIC3254 CODEC?
Regards,Collin WellsPrecision ADC Applications
The miniDSP_D_Cycles and miniDSP_A_Cycles property in PuerPath Studio are the number of cycles allocated per word clock frame. The lower the number of cycles per frame, the lesser power consumption.
In PurePath Studio, the cycles are set according to the amount of processing required. If the code is compiled and there is an error showing that the resources are exceeded, increase the number of cycles. Likewise, if you set the cycles to 904 and you have little processing in the process flow, you can reduce the number of cycles to reduce power consumption.
In terms of the device register map, the cycles shown is PurePath is the same as the IDAC and IADC values. PurePath has a macro in the SystemSettingsCode property of the framework that automatically configures IDAC/IADC based on the miniDSP_D_Cycles/miniDSP_A_Cycles, respectively. Also, there is another macro that will set the interpolation and decimation factors depending on the framework. For example, the AIC3254_8x4x franework will configure Interp and Decim to 8 and 4, respectively.
Also, IDAC and IADC must be an integral multiple of the interpolation and decimation factors, respectively. PurePath does quantize IDAC/IADC automatically in the property window to accomodate this restriction.
In general, the main restriction in terms of configuration is that IDAC>=MDAC*DOSR and IADC>=MADC*AOSR.
Other than that, there are cases where sync mode is required for the miniDSP. At the moment of this writing, there are no components in the GDE that require this mode. Nevertheless, the restrictions are described in the design note below. As long as p0_r60_b7 is '0', then these restrictions do not apply.
Also, below is some information on C-RAM and I-RAM access for reference:
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