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PCM5142: saturation problem

Part Number: PCM5142
Other Parts Discussed in Thread: CC2564

Hi 

I'am using PCM5142 on my own board. and I programmed pcm5142 with pure path studio

My problem is when I using EQ  in pure path studio, if I volume up in android, output is saturated. 

But, when I don't use PPS( just initialize pcm5142 set),  if I volume up in android, output is not saturated.

Why does saturation occur with EQ or PPS ? 

This is my process in pps. 

  • Hi Minkyo,

    Can you clarify what you mean when you say "saturated"? Do you mean the output is clipping? What is the analog behavior you are seeing if you were to play a tone?

    Thanks,
    Paul
  • Thank you for the reply!!

    This is scope picture when I just set pcm5142 clk.

    and this is scope picture when I set set pcm5142 with PPS to use EQ

    Why does saturation occur at different voltage levels?

    also if I raise the EQ level, the signal is shown below.




    what is my problem?

    Please give me details. Thanks!!


  • Hi Minkyo,

    I tested the same process flow on my bench I do not have any issues with clipping/saturation (unless I put max gain on a band). I do not know why your output is less than 1Vpp during this test. Can you share an image of the position you have the GEQ set to during the event? In general I would recommend starting with an attenuated input signal when using an EQ, as it is unrealistic to expect a full scale sine wave (or all energy in a single band).

    Thanks,
    Paul
  • new 1.txt
    /// This is PCM5142 init buffer
    
    const reg_value miniDSP_D_reg_values[] = {
    
    //////////////////////////////////////////////////////////////
    ////////////////// DAC reset, clock set
    
    {  0,0x00}, //PAGE 0 select
    {  1,0x11}, // Reset
    { 37,0x7F}, //Disable all clock missing detectors and clock auto mode
    
    
    //  PLLCK = (CLK) x R x (J.D)       11.28 * 1 *16
    //          ------------------  == --------------  = 90.24MHz
    //               P                      2
    // CLK = SCK = 11.28MHz
    
    //{ 13,0x00},  // DAC PLL source clock ( 000 : SCK)
    {13,0x10}, //slave
    { 14,0x10}, // DAC clock source PLL clock
    //{ 20,0x01}, // P value (2)
    {20,0x00}, //slave
    
    { 21,0x10}, // J value (16)
    
    { 22,0x00}, // 22,23 D value (0)
    { 23,0x00},
    //{ 24,0x00}, //R value(1)
    {24,0x01}, // slave
    
    // DSP CLK = PLLCK/DDSP = 90.24 / 2 = 45.12MHz
    //
    { 27,0x01},// DDSP (2)
    //
    // DAC CLK = PLLCK/DDAC = 90.24 / 16 = 5.64MHz
    //
    { 28,0x0f}, // DDAC (16)
    //
    // CP(charge pump) Clock = DAC CLK / NCP = 5.64MHz / 4 = 1.41MHz
    //
    { 29,0x03}, // NCP (4)
    //
    // Oversampling Ratio clock = DAC CLK /DOSR = 5.64MHz / 8 = 705KHz
    //
    { 30,0x08}, // DOSR (8)
    
    //{  4,0x01},  // return error 발생으로 주석처리 (default 값이 1임) PLL enable
    
    { 40,0x00}, // I2S Format I2S 16bits
    { 41,0x01}, // I2S Shift 1 BCK
    { 42,0x11}, // Left, Right DAC Data Path
    //{  9,0x31}, // DAC Master Mode : BCK invert, BCK, SRKO output enable //31
    { 9,0x00},
    //  SCK = 11.28MHz  BCK = 2.82MHz  FS=2.82MHz/64=44.1KHz <- 8530 BCK - SCK connection
    //{ 12,0x03}, // Master Mode BCK, LRCK divider functional
    { 12,0x00},
    // BCK = SCK / DSLRK = 11.28 / 4 = 2.82MHz
    { 32,0x03}, // DSLRK(4)
    //{ 32,0x00},
    //
    //  LRCK = BCK / DLRK = 2.82 / 64 = 44.1KHz
    { 33,0x3f}, // DLRK (64)
    //{33,0x00},
    { 35,0x04}, // IDSP
    { 36,0x00},
    
    { 60,0x01}, // Right channel volume follows left channel setting
    { 61,120}, //vol 0dB
    
    //{  0,0x01},
    //{  3,0x4},
    
    {  0,0x00},
    {  3,0x11}, // left/right mute
    {  2,0x01}, // system standby mode
    
    #if 0
    {  2,0x00},
    {  3,0x00}
    /////////////////////////////////////////////////////////////
    //mini DSP
    #else
    {  0,0x2C},
    {  8,0x00},
    {  9,0x00},
    { 10,0x00},
    { 11,0x00},
    { 12,0x00},
    { 13,0x00},
    { 14,0x00},
    { 15,0x00},
    { 16,0x00},
    { 17,0x00},
    { 18,0x00},
    { 19,0x00},
    { 20,0x00},
    { 21,0x00},
    { 22,0x00},
    { 23,0x00},
    { 24,0x00},
    { 25,0x00},
    { 26,0x00},
    { 27,0x00},
    { 28,0xFF},
    { 29,0xFF},
    { 30,0xFF},
    { 31,0x00},
    { 32,0x80},
    { 33,0x00},
    { 34,0x00},
    { 35,0x00},
    { 36,0x40},
    { 37,0x00},
    { 38,0x00},
    { 39,0x00},
    { 40,0x7F},
    { 41,0xFF},
    { 42,0xFF},
    { 43,0x00},
    { 44,0x00},
    { 45,0x00},
    { 46,0x00},
    { 47,0x00},
    { 48,0xB8},
    { 49,0x8C},
    { 50,0x96},
    { 51,0x00},
    { 52,0x6B},
    { 53,0x2D},
    { 54,0x1E},
    { 55,0x00},
    { 56,0x5C},
    { 57,0x46},
    { 58,0x4B},
    { 59,0x00},
    { 60,0x15},
    { 61,0x55},
    { 62,0x55},
    { 63,0x00},
    { 64,0x60},
    { 65,0x00},
    { 66,0x00},
    { 67,0x00},
    { 68,0x00},
    { 69,0x00},
    { 70,0x00},
    { 71,0x00},
    { 72,0xE0},
    { 73,0x00},
    { 74,0x00},
    { 75,0x00},
    { 76,0x80},
    { 77,0x00},
    { 78,0x00},
    { 79,0x00},
    { 80,0x60},
    { 81,0x00},
    { 82,0x00},
    { 83,0x00},
    { 84,0x40},
    { 85,0x00},
    { 86,0x00},
    { 87,0x00},
    { 88,0x7F},
    { 89,0xB2},
    { 90,0x60},
    { 91,0x00},
    { 92,0x20},
    { 93,0x00},
    { 94,0x00},
    { 95,0x00},
    { 96,0x20},
    { 97,0xDA},
    { 98,0x4D},
    { 99,0x00},
    {100,0x00},
    {101,0x00},
    {102,0x00},
    {103,0x00},
    {104,0xC0},
    {105,0x94},
    {106,0x1B},
    {107,0x00},
    {108,0x1E},
    {109,0x93},
    {110,0x3D},
    {111,0x00},
    {112,0x00},
    {113,0x00},
    {114,0x00},
    {115,0x00},
    {116,0x00},
    {117,0x00},
    {118,0x00},
    {119,0x00},
    {120,0x3F},
    {121,0x6B},
    {122,0xE5},
    {123,0x00},
    {124,0xE0},
    {125,0x92},
    {126,0x75},
    {127,0x00},
    {  0,0x2D},
    {  8,0x00},
    {  9,0x00},
    { 10,0x00},
    { 11,0x00},
    { 12,0x22},
    { 13,0x8B},
    { 14,0xE0},
    { 15,0x00},
    { 16,0x00},
    { 17,0x00},
    { 18,0x00},
    { 19,0x00},
    { 20,0xC1},
    { 21,0xC6},
    { 22,0xF7},
    { 23,0x00},
    { 24,0x1B},
    { 25,0xBE},
    { 26,0xC8},
    { 27,0x00},
    { 28,0x00},
    { 29,0x00},
    { 30,0x00},
    { 31,0x00},
    { 32,0x00},
    { 33,0x00},
    { 34,0x00},
    { 35,0x00},
    { 36,0x3E},
    { 37,0x39},
    { 38,0x09},
    { 39,0x00},
    { 40,0xE1},
    { 41,0xB5},
    { 42,0x58},
    { 43,0x00},
    { 44,0x00},
    { 45,0x00},
    { 46,0x00},
    { 47,0x00},
    { 48,0x27},
    { 49,0xE9},
    { 50,0x74},
    { 51,0x00},
    { 52,0x00},
    { 53,0x00},
    { 54,0x00},
    { 55,0x00},
    { 56,0xC5},
    { 57,0xE7},
    { 58,0x1F},
    { 59,0x00},
    { 60,0x12},
    { 61,0xC7},
    { 62,0xAB},
    { 63,0x00},
    { 64,0x00},
    { 65,0x00},
    { 66,0x00},
    { 67,0x00},
    { 68,0x00},
    { 69,0x00},
    { 70,0x00},
    { 71,0x00},
    { 72,0x3A},
    { 73,0x18},
    { 74,0xE1},
    { 75,0x00},
    { 76,0xE5},
    { 77,0x4E},
    { 78,0xE0},
    { 79,0x00},
    { 80,0x00},
    { 81,0x00},
    { 82,0x00},
    { 83,0x00},
    { 84,0x34},
    { 85,0xF0},
    { 86,0xF8},
    { 87,0x00},
    { 88,0x00},
    { 89,0x00},
    { 90,0x00},
    { 91,0x00},
    { 92,0xD3},
    { 93,0x78},
    { 94,0x36},
    { 95,0x00},
    { 96,0xFD},
    { 97,0x02},
    { 98,0x5C},
    { 99,0x00},
    {100,0x00},
    {101,0x00},
    {102,0x00},
    {103,0x00},
    {104,0x00},
    {105,0x00},
    {106,0x00},
    {107,0x00},
    {108,0x2C},
    {109,0x87},
    {110,0xCA},
    {111,0x00},
    {112,0xEE},
    {113,0x0C},
    {114,0xAC},
    {115,0x00},
    {116,0x00},
    {117,0x00},
    {118,0x00},
    {119,0x00},
    {120,0x51},
    {121,0xDD},
    {122,0xFE},
    {123,0x00},
    {124,0x00},
    {125,0x00},
    {126,0x00},
    {127,0x00},
    {  0,0x2E},
    {  8,0xFB},
    {  9,0x8E},
    { 10,0x24},
    { 11,0x00},
    { 12,0xCC},
    { 13,0xAD},
    { 14,0x4F},
    { 15,0x00},
    { 16,0x00},
    { 17,0x00},
    { 18,0x00},
    { 19,0x00},
    { 20,0x00},
    { 21,0x00},
    { 22,0x00},
    { 23,0x00},
    { 24,0x04},
    { 25,0x71},
    { 26,0xDC},
    { 27,0x00},
    { 28,0x01},
    { 29,0x74},
    { 30,0xB3},
    { 31,0x00},
    { 32,0x00},
    { 33,0x00},
    { 34,0x00},
    { 35,0x00},
    { 36,0x00},
    { 37,0x00},
    { 38,0x00},
    { 39,0x00},
    { 40,0x00},
    { 41,0x00},
    { 42,0x00},
    { 43,0x00},
    { 44,0xC0},
    { 45,0x00},
    { 46,0x00},
    { 47,0x00},
    { 48,0x0C},
    { 49,0x40},
    { 50,0x00},
    { 51,0x00},
    { 52,0x1F},
    { 53,0x40},
    { 54,0x00},
    { 55,0x00},
    {  0,0x3E},
    {  8,0x00},
    {  9,0x00},
    { 10,0x00},
    { 11,0x00},
    { 12,0x00},
    { 13,0x00},
    { 14,0x00},
    { 15,0x00},
    { 16,0x00},
    { 17,0x00},
    { 18,0x00},
    { 19,0x00},
    { 20,0x00},
    { 21,0x00},
    { 22,0x00},
    { 23,0x00},
    { 24,0x00},
    { 25,0x00},
    { 26,0x00},
    { 27,0x00},
    { 28,0xFF},
    { 29,0xFF},
    { 30,0xFF},
    { 31,0x00},
    { 32,0x80},
    { 33,0x00},
    { 34,0x00},
    { 35,0x00},
    { 36,0x40},
    { 37,0x00},
    { 38,0x00},
    { 39,0x00},
    { 40,0x7F},
    { 41,0xFF},
    { 42,0xFF},
    { 43,0x00},
    { 44,0x00},
    { 45,0x00},
    { 46,0x00},
    { 47,0x00},
    { 48,0xB8},
    { 49,0x8C},
    { 50,0x96},
    { 51,0x00},
    { 52,0x6B},
    { 53,0x2D},
    { 54,0x1E},
    { 55,0x00},
    { 56,0x5C},
    { 57,0x46},
    { 58,0x4B},
    { 59,0x00},
    { 60,0x15},
    { 61,0x55},
    { 62,0x55},
    { 63,0x00},
    { 64,0x60},
    { 65,0x00},
    { 66,0x00},
    { 67,0x00},
    { 68,0x00},
    { 69,0x00},
    { 70,0x00},
    { 71,0x00},
    { 72,0xE0},
    { 73,0x00},
    { 74,0x00},
    { 75,0x00},
    { 76,0x80},
    { 77,0x00},
    { 78,0x00},
    { 79,0x00},
    { 80,0x60},
    { 81,0x00},
    { 82,0x00},
    { 83,0x00},
    { 84,0x40},
    { 85,0x00},
    { 86,0x00},
    { 87,0x00},
    { 88,0x7F},
    { 89,0xB2},
    { 90,0x60},
    { 91,0x00},
    { 92,0x20},
    { 93,0x00},
    { 94,0x00},
    { 95,0x00},
    { 96,0x20},
    { 97,0xDA},
    { 98,0x4D},
    { 99,0x00},
    {100,0x00},
    {101,0x00},
    {102,0x00},
    {103,0x00},
    {104,0xC0},
    {105,0x94},
    {106,0x1B},
    {107,0x00},
    {108,0x1E},
    {109,0x93},
    {110,0x3D},
    {111,0x00},
    {112,0x00},
    {113,0x00},
    {114,0x00},
    {115,0x00},
    {116,0x00},
    {117,0x00},
    {118,0x00},
    {119,0x00},
    {120,0x3F},
    {121,0x6B},
    {122,0xE5},
    {123,0x00},
    {124,0xE0},
    {125,0x92},
    {126,0x75},
    {127,0x00},
    {  0,0x3F},
    {  8,0x00},
    {  9,0x00},
    { 10,0x00},
    { 11,0x00},
    { 12,0x22},
    { 13,0x8B},
    { 14,0xE0},
    { 15,0x00},
    { 16,0x00},
    { 17,0x00},
    { 18,0x00},
    { 19,0x00},
    { 20,0xC1},
    { 21,0xC6},
    { 22,0xF7},
    { 23,0x00},
    { 24,0x1B},
    { 25,0xBE},
    { 26,0xC8},
    { 27,0x00},
    { 28,0x00},
    { 29,0x00},
    { 30,0x00},
    { 31,0x00},
    { 32,0x00},
    { 33,0x00},
    { 34,0x00},
    { 35,0x00},
    { 36,0x3E},
    { 37,0x39},
    { 38,0x09},
    { 39,0x00},
    { 40,0xE1},
    { 41,0xB5},
    { 42,0x58},
    { 43,0x00},
    { 44,0x00},
    { 45,0x00},
    { 46,0x00},
    { 47,0x00},
    { 48,0x27},
    { 49,0xE9},
    { 50,0x74},
    { 51,0x00},
    { 52,0x00},
    { 53,0x00},
    { 54,0x00},
    { 55,0x00},
    { 56,0xC5},
    { 57,0xE7},
    { 58,0x1F},
    { 59,0x00},
    { 60,0x12},
    { 61,0xC7},
    { 62,0xAB},
    { 63,0x00},
    { 64,0x00},
    { 65,0x00},
    { 66,0x00},
    { 67,0x00},
    { 68,0x00},
    { 69,0x00},
    { 70,0x00},
    { 71,0x00},
    { 72,0x3A},
    { 73,0x18},
    { 74,0xE1},
    { 75,0x00},
    { 76,0xE5},
    { 77,0x4E},
    { 78,0xE0},
    { 79,0x00},
    { 80,0x00},
    { 81,0x00},
    { 82,0x00},
    { 83,0x00},
    { 84,0x34},
    { 85,0xF0},
    { 86,0xF8},
    { 87,0x00},
    { 88,0x00},
    { 89,0x00},
    { 90,0x00},
    { 91,0x00},
    { 92,0xD3},
    { 93,0x78},
    { 94,0x36},
    { 95,0x00},
    { 96,0xFD},
    { 97,0x02},
    { 98,0x5C},
    { 99,0x00},
    {100,0x00},
    {101,0x00},
    {102,0x00},
    {103,0x00},
    {104,0x00},
    {105,0x00},
    {106,0x00},
    {107,0x00},
    {108,0x2C},
    {109,0x87},
    {110,0xCA},
    {111,0x00},
    {112,0xEE},
    {113,0x0C},
    {114,0xAC},
    {115,0x00},
    {116,0x00},
    {117,0x00},
    {118,0x00},
    {119,0x00},
    {120,0x51},
    {121,0xDD},
    {122,0xFE},
    {123,0x00},
    {124,0x00},
    {125,0x00},
    {126,0x00},
    {127,0x00},
    {  0,0x40},
    {  8,0xFB},
    {  9,0x8E},
    { 10,0x24},
    { 11,0x00},
    { 12,0xCC},
    { 13,0xAD},
    { 14,0x4F},
    { 15,0x00},
    { 16,0x00},
    { 17,0x00},
    { 18,0x00},
    { 19,0x00},
    { 20,0x00},
    { 21,0x00},
    { 22,0x00},
    { 23,0x00},
    { 24,0x04},
    { 25,0x71},
    { 26,0xDC},
    { 27,0x00},
    { 28,0x01},
    { 29,0x74},
    { 30,0xB3},
    { 31,0x00},
    { 32,0x00},
    { 33,0x00},
    { 34,0x00},
    { 35,0x00},
    { 36,0x00},
    { 37,0x00},
    { 38,0x00},
    { 39,0x00},
    { 40,0x00},
    { 41,0x00},
    { 42,0x00},
    { 43,0x00},
    { 44,0xC0},
    { 45,0x00},
    { 46,0x00},
    { 47,0x00},
    { 48,0x0C},
    { 49,0x40},
    { 50,0x00},
    { 51,0x00},
    { 52,0x1F},
    { 53,0x40},
    { 54,0x00},
    { 55,0x00},
    {  0,0x98},
    {  8,0x00},
    {  9,0x00},
    { 10,0x00},
    { 11,0x00},
    { 12,0x00},
    { 13,0x00},
    { 14,0x00},
    { 15,0x00},
    { 16,0x00},
    { 17,0x10},
    { 18,0x00},
    { 19,0x00},
    { 20,0x00},
    { 21,0x10},
    { 22,0x04},
    { 23,0x01},
    { 24,0x00},
    { 25,0x60},
    { 26,0x03},
    { 27,0xFB},
    { 28,0x00},
    { 29,0x70},
    { 30,0x3B},
    { 31,0xFB},
    { 32,0x00},
    { 33,0x00},
    { 34,0x00},
    { 35,0x00},
    { 36,0x00},
    { 37,0x90},
    { 38,0x34},
    { 39,0x00},
    { 40,0x00},
    { 41,0x00},
    { 42,0x00},
    { 43,0x00},
    { 44,0x00},
    { 45,0x60},
    { 46,0x2F},
    { 47,0xFB},
    { 48,0x00},
    { 49,0x40},
    { 50,0x08},
    { 51,0x26},
    { 52,0x00},
    { 53,0x80},
    { 54,0x3C},
    { 55,0x04},
    { 56,0x00},
    { 57,0x70},
    { 58,0x28},
    { 59,0x26},
    { 60,0x00},
    { 61,0x00},
    { 62,0x00},
    { 63,0x00},
    { 64,0x00},
    { 65,0x90},
    { 66,0x3C},
    { 67,0x00},
    { 68,0x00},
    { 69,0x70},
    { 70,0x33},
    { 71,0xFB},
    { 72,0x00},
    { 73,0x00},
    { 74,0x00},
    { 75,0x00},
    { 76,0x00},
    { 77,0x90},
    { 78,0x3C},
    { 79,0x00},
    { 80,0x00},
    { 81,0x70},
    { 82,0x47},
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    {121,0x6F},
    {122,0xEC},
    {123,0x32},
    {124,0x00},
    {125,0x30},
    {126,0x00},
    {127,0x02},
    {  0,0xA6},
    {  8,0x00},
    {  9,0x30},
    { 10,0x00},
    { 11,0x02},
    { 12,0x00},
    { 13,0x6F},
    { 14,0xEC},
    { 15,0x33},
    { 16,0x00},
    { 17,0x6F},
    { 18,0xEC},
    { 19,0x34},
    { 20,0x00},
    { 21,0x30},
    { 22,0x00},
    { 23,0x02},
    { 24,0x00},
    { 25,0x30},
    { 26,0x00},
    { 27,0x02},
    { 28,0x00},
    { 29,0x6F},
    { 30,0xEC},
    { 31,0x35},
    { 32,0x00},
    { 33,0x6F},
    { 34,0xEC},
    { 35,0x36},
    { 36,0x00},
    { 37,0x30},
    { 38,0x00},
    { 39,0x02},
    { 40,0x00},
    { 41,0x30},
    { 42,0x00},
    { 43,0x02},
    { 44,0x00},
    { 45,0x6F},
    { 46,0xEC},
    { 47,0x37},
    { 48,0x00},
    { 49,0x6F},
    { 50,0xEC},
    { 51,0x38},
    { 52,0x00},
    { 53,0x30},
    { 54,0x00},
    { 55,0x02},
    { 56,0x00},
    { 57,0x30},
    { 58,0x00},
    { 59,0x02},
    { 60,0x00},
    { 61,0x6F},
    { 62,0xF0},
    { 63,0x7D},
    { 64,0x00},
    { 65,0x6F},
    { 66,0xF0},
    { 67,0x7E},
    { 68,0x00},
    { 69,0x30},
    { 70,0x04},
    { 71,0x02},
    { 72,0x00},
    { 73,0x30},
    { 74,0x04},
    { 75,0x02},
    { 76,0x00},
    { 77,0x6F},
    { 78,0xF0},
    { 79,0x7F},
    { 80,0x00},
    { 81,0x6F},
    { 82,0xF0},
    { 83,0x80},
    { 84,0x00},
    { 85,0x30},
    { 86,0x04},
    { 87,0x02},
    { 88,0x00},
    { 89,0x30},
    { 90,0x04},
    { 91,0x02},
    { 92,0x00},
    { 93,0x6F},
    { 94,0xF0},
    { 95,0x81},
    { 96,0x00},
    { 97,0x6F},
    { 98,0xF0},
    { 99,0x82},
    {100,0x00},
    {101,0x30},
    {102,0x04},
    {103,0x02},
    {104,0x00},
    {105,0x30},
    {106,0x04},
    {107,0x02},
    {108,0x00},
    {109,0x6F},
    {110,0xF0},
    {111,0x83},
    {112,0x00},
    {113,0x6F},
    {114,0xF0},
    {115,0x84},
    {116,0x00},
    {117,0x30},
    {118,0x04},
    {119,0x02},
    {120,0x00},
    {121,0x30},
    {122,0x04},
    {123,0x02},
    {124,0x01},
    {125,0x10},
    {126,0x03},
    {127,0xFF},
    
    //////////////////////////////////////////////////////////////
    //run code from RAM
    {  0,0x00},
    { 43,0x1f},
    ////////////////////////////////////////////////////////////
    //16x, 8x
    { 34,0x00},
    
    ////////////////////////////////////////////////////////////
    //Enable adaptive mode for DAC
    {  0,0x2C},
    {  1,0x00},
    {  1,0x04},
    ///////////////////////////////////////////////////////////////
    //Normal mode DAC
    {  0,0x00},
    {  2,0x00}, //Stanby -> Normal operation
    {  3,0x00}  // Mute remove
    #endif
    
    
    };
    
    
    
    //This is EQ control code 
    
    else if(nMSP_State == EQ_CON_ST)
    {
    	if(Command_Step == 0)
    	{
    		DAC_Write(I2C_VOICE_DAC_ADDR,0,44); // DAC Reg page 44 으로 변환
    		Command_Step = 1;
    	}
    	else if(Command_Step == 1)
    	{
    		if(dataLength == 0)
    		{
    			I2C_Tx_Int_Disable(); // 전송 완료 대기
    			Command_Step = 2;
    		}
    
    	}
    	else if(Command_Step == 2)
    	{
    		DAC_Write(I2C_VOICE_DAC_ADDR,Regaddr,MSP_ReadBuff[3]);
    		Command_Step = 3;
    	}
    	else if(Command_Step == 3)
    	{
    		if(dataLength == 0)
    		{
    			I2C_Tx_Int_Disable(); // 전송 완료 대기
    			Command_Step = 4;
    		}
    
    	}
    	else if(Command_Step == 4)
    	{
    		if(dataLength == 0)
    		{
    			DAC_Write(I2C_VOICE_DAC_ADDR,0,62);
    			Command_Step = 5;
    		}
    
    	}
    	else if(Command_Step == 5)
    	{
    		if(dataLength == 0)
    		{
    			I2C_Tx_Int_Disable(); // 전송 완료 대기
    			Command_Step = 6;
    		}
    
    	}
    	else if(Command_Step == 6)
    	{
    		DAC_Write(I2C_VOICE_DAC_ADDR,Regaddr,MSP_ReadBuff[3]);
    		Command_Step = 7;
    	}
    	else if(Command_Step == 7)
    	{
    		if(dataLength == 0)
    		{
    			I2C_Tx_Int_Disable(); // 전송 완료 대기
    			Command_Step = 8;
    		}
    	}
    	else if(Command_Step == 8)
    	{
    		if(dataLength == 0)
    		{
    			DAC_Write(I2C_VOICE_DAC_ADDR,0,44);
    			Command_Step = 9;
    		}
    
    	}
    	else if(Command_Step == 9)
    	{
    		if(dataLength == 0)
    		{
    			I2C_Tx_Int_Disable(); // 전송 완료 대기
    			Command_Step = 10;
    		}
    
    	}
    	else if(Command_Step == 10)
    	{
    		DAC_Write(I2C_VOICE_DAC_ADDR,1,5);
    		Command_Step = 10;
    	}
    Thank you for the reply

    I attached  PCM5142 init code and EQ control code.

    Please check....

  • Hi Paul,

    I added Page 1 Reg 3 = 0x4

    and it solved 1Vpp clipping.

    In datasheet, There is no information about Page 1 Reg3. What are the settings for?

    Also, when I max  5 Eq bands, It still showed saturation.

    Could you give me some tips?

    Thank you !!

  • Hi Minkyo,

    I think we need to take a step back and look at the whole system.
    1. Is this a custom board or the EVM? Can you share the schematic if it is a custom board?
    2. What is your hardware clock configuration? In you initialization code you are configuring the PLL, but it seems like you have valid clocks already? Is SCK connected? What is SCK, BCK, and LRCK frequencies?

    I suspect that you have some issue with your charge pump, so the negative supply is not being established.

    The page 1 register 3 value that you are writing to changes the delay in the charge pump startup, but I do not recommend that you use this register. We marked it reserved.

    The most recent image you shared is just showing the output clipping at the DAC's full-scale value. The maximum signal the DAC can produce is 2.1Vrms or 6Vpeak-peak. The equalizer will allow a high digital gain, but that does not mean that DAC can reproduce it. You input signal is probably a 0dBFS tone, which is unrealistic for music.

    Thanks,
    Paul
  • Hi Paul, Thank you for the reply.

    1. This is custom.

    2. SCK is disconnected. 

        BCK = 3.53MHz

        LRCK = 44.1KHz

    Is there some mistake?

  • To confirm, your BCK is ~81×fS? Is this clock continuous, or is it some kind of limited duty cycle? If the BCK is not continuous, it cannot be used as the source for the PLL.

    Thanks,
    Paul
  • Any updates?
  • Hi Paul.

    Sorry for the delay.

    Actually, PCM5142 is connected CC2564.

    and CC2564 I2S Clock can be modfied by KHz unit.(processors.wiki.ti.com/.../CC256x_VS_HCI_Commands

    but PCM5142 recommanded clock is 1.4112, 2.8224, 5.6448, 8.4672 MHz for 44.1KHz sample frequency.(pcm5142 data sheet P109)

    How Can I match 2 devices I2S format?
  • I will change PLL clock and I will reply again. Thank you.
  • Hi Minkyo,

    I believe you are on the correct path. Setting the CC device to have a correct BCK is key for 3-wire operation.

    Thanks,
    Paul
  • Hi Paul.

    I modified BCK clock to 2.8224MHz, and Fs = 44.1KHz

    also I set it the same as the I2S format of PCM5142.

    When I play 440Hz, DAC output FFT result is below picture. 

    why 1KHz ~ 2.6KHz Peak  is there? when I listen through speaker. I can feel high frequency. 

    Could you tell me my mistake??

    and I set clocks 

    // PLLCK = (CLK) x R x (J.D)       2.8224 * 2 *16
    //                   ------------------     = --------------------- = 90.3168MHz
    //                            P                         1
    // CLK = BCK = 2.8224MHz

    DSP CLK = PLL / DDSP = 90.3168 / 2 = 45.1584MHz

    DAC CLK = PLL/DDAC = 90.3168 / 16 = 5.6448MHz

    CP(charge pump) Clock = DAC CLK / NCP = 5.6448MHz/4 = 1.4112MHz

    Oversampling Ratio Clock = DAC CLK / DOSR = 5.64MHz /8 =705.6KHz

    I2S data size = 16bit

    I2S Shift 1 BCK

  • If I play other frequency, peak changed
  • Hi Minkyo,

    I am not sure what you are experiencing here.  But can you clarify the following:

    Why are you configuring the PLL at all? You are using 44.1kHz, with BCK = 64*fS, so you are already using a supported auto-detect sample rate:

    Try commenting out your PLL configuration code, as that will quickly let us know if you have some issue with the PLL configuration.  Does the analog output still have the glitches you posted earlier?

    In addition, by default the device is configured to use I2S.  You are not required to input the 1 bit offset, as I2S is defined as having the data start with the 1bit offset.  I would comment the command where you set the AOFS register as well.

    Thanks,

    Paul

  • Hi Paul.

    This is my DAC set code.

    The Glitch is fine.



    const reg_value miniDSP_D_reg_values[] = { ////////////////////////////////////////////////////////////// ////////////////// DAC reset, clock set { 0,0x00}, //PAGE 0 select { 2,0x01}, // system standby mode { 1,0x11}, // Reset { 37,0x7F}, //Disable all clock missing detectors and clock auto mode // PLLCK = (CLK) x R x (J.D) 2.8224 * 2 *16 // ------------------ == -------------- = 90.3168MHz // P 1 // CLK = BCK = 2.8224 { 13,0x10}, // PLL clock source = BCK { 14,0x10}, // DAC clock source PLL clock { 4,0x01}, // PLL enable { 20,0x00}, //P value = 1 { 21,0x10}, // J value = 16 { 22,0x00}, // 22,23 D value (0) { 23,0x00}, { 24,0x01}, // R value = 2 // DSP CLK = PLLCK/DDSP = 90.3168 / 2 = 45.1584MHz // { 27,0x01},// DDSP (2) // // DAC CLK = PLLCK/DDAC = 90.3168 / 16 = 5.6448MHz // { 28,0x0f}, // DDAC (16) // // CP(charge pump) Clock = DAC CLK / NCP = 5.6448MHz / 4 = 1.4112MHz // { 29,0x03}, // NCP (4) // // Oversampling Ratio clock = DAC CLK /DOSR = 5.64MHz / 8 = 705.6KHz // { 30,0x07}, // DOSR (8) { 40,0x00}, // I2S Format I2S 16bits //{ 41,0x00}, // I2S Shift 1 BCK { 42,0x11}, // Left, Right DAC Data Path { 9,0x00}, { 12,0x03}, // Master Mode BCK, LRCK divider functional { 35,0x04}, // IDSP =1024 { 36,0x00}, { 60,0x01}, // Right channel volume follows left channel setting { 61,120}, // { 0,0x01}, { 3,0x4}, { 0,0x00}, { 3,0x11}, // left/right mute .... miniDSP coef & instructions.... ////////////////////////////////////////////////////////////// //run code from RAM { 0,0x00}, { 43,0x1f}, //////////////////////////////////////////////////////////// //16x, 8x { 34,0x10}, //////////////////////////////////////////////////////////// //Enable adaptive mode for DAC { 0,0x2C}, { 1,0x00}, { 1,0x04}, /////////////////////////////////////////////////////////////// //Normal mode DAC { 0,0x00}, { 2,0x00}, //Stanby -> Normal operation { 3,0x00} // Mute remove

    Still listen high frequency...

  • Hi Minkyo,

    I think you have some issues with the DSP, as you have enabled the 16x interpolation mode.  Enabling the 16x interpolation mode has some implications on the clock tree as well the DSP requirements, so I do not recommend it for custom process flows.  I have commented the code you sent with some changes that I would make.  I was not able to recreate the 1kHz-2.6kHz components, but that might also be dependent on the process flow you have created.  Using a default process flow I saw strange behavior, with ~10kHz spurs.  

    {  0,0x00}, //PAGE 0 select
    {  2,0x01}, // system standby mode
    {  1,0x11}, // Reset
    { 37,0x7F}, //Disable all clock missing detectors and clock auto mode
    
    
    //  PLLCK = (CLK) x R x (J.D)       2.8224 * 2 *16
    //          ------------------  == --------------  = 90.3168MHz
    //               P                      1
    // CLK = BCK = 2.8224
    
    { 13,0x10}, // PLL clock source = BCK
    //{ 14,0x10}, // DAC clock source PLL clock - TI: Not necessary
    
    {  4,0x01},  // PLL enable
    
    { 20,0x00}, //P value = 1
    { 21,0x10}, // J value = 16
    { 22,0x00}, // 22,23 D value (0)
    { 23,0x00},
    
    { 24,0x01}, // R value = 2
    
    // DSP CLK = PLLCK/DDSP = 90.3168 / 2 = 45.1584MHz
    //
    { 27,0x01},// DDSP (2)
    //
    // DAC CLK = PLLCK/DDAC = 90.3168 / 16 = 5.6448MHz
    //
    { 28,0x0f}, // DDAC (16)
    //
    // CP(charge pump) Clock = DAC CLK / NCP = 5.6448MHz / 4 = 1.4112MHz
    //
    { 29,0x03}, // NCP (4)
    //
    // Oversampling Ratio clock = DAC CLK /DOSR = 5.64MHz / 8 = 705.6KHz
    //
    { 30,0x07}, // DOSR (8)
    
    
    { 40,0x00}, // I2S Format I2S 16bits
    //{ 41,0x00}, // I2S Shift 1 BCK
    //{ 42,0x11}, // Left, Right DAC Data Path  - TI:not necessary
    //{  9,0x00}, - TI:not necessary
    //{ 12,0x03}, // Master Mode BCK, LRCK divider functional- TI:not necessary
    
    { 35,0x04}, // IDSP =1024
    { 36,0x00},
    
    { 60,0x01}, // Right channel volume follows left channel setting
    { 61,120}, //
    
    //{  0,0x01},- TI:not recommended
    //{  3,0x4},- TI:not recommended
    
    {  0,0x00},
    {  3,0x11}, // left/right mute
    
    
    .... miniDSP coef & instructions....
    
    //////////////////////////////////////////////////////////////
    //run code from RAM
    {  0,0x00},
    { 43,0x1f},
    ////////////////////////////////////////////////////////////
    //16x, 8x
    //{ 34,0x10}, TI: Original
    { 34,0x00} //TI: It is not recommended to change the interpolator to 16x in this case.  This have greater impact on the DSP and the number of instructions that can be supported.
    ////////////////////////////////////////////////////////////
    //Enable adaptive mode for DAC
    {  0,0x2C},
    {  1,0x00},
    {  1,0x04},
    ///////////////////////////////////////////////////////////////
    //Normal mode DAC
    {  0,0x00},
    {  2,0x00}, //Stanby -> Normal operation
    {  3,0x00}  // Mute remove

    Please disable the 16x and see if you still have issues.

    Thanks,

    Paul

    PCM5142 Configuration with Pauls comments.txt
    {  0,0x00}, //PAGE 0 select
    {  2,0x01}, // system standby mode
    {  1,0x11}, // Reset
    { 37,0x7F}, //Disable all clock missing detectors and clock auto mode
    
    
    //  PLLCK = (CLK) x R x (J.D)       2.8224 * 2 *16
    //          ------------------  == --------------  = 90.3168MHz
    //               P                      1
    // CLK = BCK = 2.8224
    
    { 13,0x10}, // PLL clock source = BCK
    //{ 14,0x10}, // DAC clock source PLL clock - TI: Not necessary
    
    {  4,0x01},  // PLL enable
    
    { 20,0x00}, //P value = 1
    { 21,0x10}, // J value = 16
    { 22,0x00}, // 22,23 D value (0)
    { 23,0x00},
    
    { 24,0x01}, // R value = 2
    
    // DSP CLK = PLLCK/DDSP = 90.3168 / 2 = 45.1584MHz
    //
    { 27,0x01},// DDSP (2)
    //
    // DAC CLK = PLLCK/DDAC = 90.3168 / 16 = 5.6448MHz
    //
    { 28,0x0f}, // DDAC (16)
    //
    // CP(charge pump) Clock = DAC CLK / NCP = 5.6448MHz / 4 = 1.4112MHz
    //
    { 29,0x03}, // NCP (4)
    //
    // Oversampling Ratio clock = DAC CLK /DOSR = 5.64MHz / 8 = 705.6KHz
    //
    { 30,0x07}, // DOSR (8)
    
    
    { 40,0x00}, // I2S Format I2S 16bits
    //{ 41,0x00}, // I2S Shift 1 BCK
    //{ 42,0x11}, // Left, Right DAC Data Path  - TI:not necessary
    //{  9,0x00}, - TI:not necessary
    //{ 12,0x03}, // Master Mode BCK, LRCK divider functional- TI:not necessary
    
    { 35,0x04}, // IDSP =1024
    { 36,0x00},
    
    { 60,0x01}, // Right channel volume follows left channel setting
    { 61,120}, //
    
    //{  0,0x01},- TI:not recommended
    //{  3,0x4},- TI:not recommended
    
    {  0,0x00},
    {  3,0x11}, // left/right mute
    
    
    .... miniDSP coef & instructions....
    
    //////////////////////////////////////////////////////////////
    //run code from RAM
    {  0,0x00},
    { 43,0x1f},
    ////////////////////////////////////////////////////////////
    //16x, 8x
    //{ 34,0x10}, TI: Original
    { 34,0x00} //TI: It is not recommended to change the interpolator to 16x in this case.  This have greater impact on the DSP and the number of instructions that can be supported.
    ////////////////////////////////////////////////////////////
    //Enable adaptive mode for DAC
    {  0,0x2C},
    {  1,0x00},
    {  1,0x04},
    ///////////////////////////////////////////////////////////////
    //Normal mode DAC
    {  0,0x00},
    {  2,0x00}, //Stanby -> Normal operation
    {  3,0x00}  // Mute remove