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TLV320AIC3104: problem

Part Number: TLV320AIC3104

Hi,

I'm trying to use TLV320AIC3104 as an audio codec communicating by I2S in slave mode with ZYNQ. 

A audio signal is plugged to LINE1LP/LINE1LM and LEFT_LOP/LEFT_LOM differentially. The MCLK, BCLK and WCLK is provided by ZYNQ and their values are 19.2MHZ, 1024KHz and 16KHz respectively. I also shorted the DOUT and DIN signals of codec, to see the input signal of mic(LINE1LP/LINE1LM) at the output of speaker(LEFT_LOP/LEFT_LOM).

The I2C registers are below.Diagram also.

My problem is that i cannot see anything at the output of LINE1LP/LINE1LM while i feed the input LINE1LP/LINE1LM  pins with 10KHz sine signal. I check the registers value with value that i write there and they are matched.  I see something on DOUT when I power up ADC. Also, when i by-pass line1lp/line1lm signals to left_lop/left_lom i see the signal correctly. I can also bypass signal from pga to left_lop/left_lom and again i can see the signal correctly. I couldnt find the problem could you please help me?

Thank you and Best regards,

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, PAGE_SELECT, PAGE0_SELECT);

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, AUDIO_CODEC_RESET, SOFT_RESET);

/* Sample Rate and Master Clock Frequency */
audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 2, 0x44); /*0xAA = 8 khz 0x44 = 16 khz 0100: DAC fS = fS(ref)/3 */

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 4, (5<<2)); /*J value = 5*/

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 5, (1200>>6)); /* Most 8 bit of 14 Bit D*/

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 6, (1200 & 0x3F) <<2 ); /* Least 6 bit of 14 Bit D*/

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 11, 1); /*R = 1*/

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 3, 0x81); /*PLL disable P=1, Q=16?(CLKDIV_OUT) */
/* Sample Rate and Master Clock Frequency */

/* Number of Bits and Digital Audio Format */

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 8, 0x00); /*BCLK and WCLK are input pins*/

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 9, 0); /*I2S mode, Audio data word length = 16 bits */

/* Number of Bits and Digital Audio Format */


/* Signal Path Through the AIC3104 */
audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 19, 0x84); /* Route Line1LP to the Left ADC, Power up Left ADC, Fully differential mode*/

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 15, 0x00); /* Unmute Left PGA, set gain to 0 dB*/

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 7, 0x08);   /* Route Left data to Left DAC*/

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 37, 0x80); /* Power up Left DAC’s*/

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 43, 0x00); /* Unmute Left digital volume control, set gain to 0 dB*/
audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 82, 0x80); /* Route Left DAC output to Left line outs*/

audio_codec_write_data_reg(AUDIO_CODEC_TLV_320_I2C_ID, 86, 0x09); /* Power up Left line out ± (differential), set gain to 0dB*/

  • Hello Fatih,

    can you read all of the page 0 registers and send them over?

    your settings look good to me. I would expect you to have output.

    best regards,
    -Steve Wilson
  • Hello Steve,

    Thanks for your reply. The page 0 registers are all given below

    Best regards,
    Fatih

    register_2 => 0x44
    register_3 => 0x81
    register_4 => 0x14
    register_5 => 0x12
    register_6 => 0xC0
    register_7 => 0x08
    register_8 => 0x00
    register_9 => 0x00
    register_10 => 0x00
    register_11 => 0x01
    register_12 => 0x00
    register_13 => 0x00
    register_14 => 0x00
    register_15 => 0x00
    register_16 => 0x80
    register_17 => 0xFF
    register_18 => 0xFF
    register_19 => 0x84
    register_20 => 0x78
    register_21 => 0x78
    register_22 => 0x78
    register_23 => 0x78
    register_24 => 0x78
    register_25 => 0x06
    register_26 => 0x00
    register_27 => 0xFE
    register_28 => 0x00
    register_29 => 0x00
    register_30 => 0xFE
    register_31 => 0x00
    register_32 => 0x00
    register_33 => 0x00
    register_34 => 0x00
    register_35 => 0x00
    register_36 => 0xC0
    register_37 => 0x80
    register_38 => 0x00
    register_39 => 0x00
    register_40 => 0x00
    register_41 => 0x00
    register_42 => 0x00
    register_43 => 0x00
    register_44 => 0x80
    register_45 => 0x00
    register_46 => 0x00
    register_47 => 0x00
    register_48 => 0x00
    register_49 => 0x00
    register_50 => 0x00
    register_51 => 0x04
    register_52 => 0x00
    register_53 => 0x00
    register_54 => 0x00
    register_55 => 0x00
    register_56 => 0x00
    register_57 => 0x00
    register_58 => 0x04
    register_59 => 0x00
    register_60 => 0x00
    register_61 => 0x00
    register_62 => 0x00
    register_63 => 0x00
    register_64 => 0x00
    register_65 => 0x04
    register_66 => 0x00
    register_67 => 0x00
    register_68 => 0x00
    register_69 => 0x00
    register_70 => 0x00
    register_71 => 0x00
    register_72 => 0x04
    register_73 => 0x00
    register_74 => 0x00
    register_75 => 0x00
    register_76 => 0x00
    register_77 => 0x00
    register_78 => 0x00
    register_79 => 0x00
    register_80 => 0x00
    register_81 => 0x00
    register_82 => 0x80
    register_83 => 0x00
    register_84 => 0x00
    register_85 => 0x00
    register_86 => 0x0B
    register_87 => 0x00
    register_88 => 0x00
    register_89 => 0x00
    register_90 => 0x00
    register_91 => 0x00
    register_92 => 0x00
    register_93 => 0x00
    register_94 => 0x90
    register_95 => 0x00
    register_96 => 0x00
    register_97 => 0x00
    register_98 => 0x00
    register_99 => 0x00
    register_100 => 0x00
    register_101 => 0x00
    register_102 => 0x02
    register_103 => 0x00
    register_104 => 0x00
    register_105 => 0x00
    register_106 => 0x00
    register_107 => 0x00
    register_108 => 0x00
    register_109 => 0x00
  • Fatih,

    1. Is your MCLK 19.2Mhz?
    2. have you checked the I2S CLKs from the processor?

    There is nothing strange that pops out in this configuration. you've got MIC1L connected to the LEFT PGA and LEFT ADC, the Left Data is routed to the LEFT DAC, the Left DAC uses the DAC_L1 path, and feeds the LEFT_LOP/M output, everything looks good.

    best regards,
    -Steve Wilson