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What is the allowable clock jitter and noise for the input clock to the TLV320ADC and TLV320AIC products?
Regards,Collin WellsPrecision ADC Applications
We have quantified the effects of the clock jitter and phase noise on the SNR of our ADCs and DACs.
For ADC3101, AIC310x kind of devices, the typical number we need is around 100ps rms jitter for the final clock to the ADC. Assuming some performance degradation inside the device (PLL, routing, etc.,), a input clock with the following rms jitter is safe:
Beyond 100ps rms, degradation may be expected.
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