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TLV320AIC3268EVM-U: Inquiry about sound quality test and PLL setting according to Master Clock change

Part Number: TLV320AIC3268EVM-U

Hi~
We are testing the quality of the PLL settings and the resulting digital audio out.
I am testing with EVM, and I am testing it by directly connecting EVM bit clock (2.82Mhz, received from TAS1020) pin to Master Clock pin.
The input is a digital input (ASI1) input through a PC, and it is tested by connecting a speaker to the built-in Class Amp.
The register related to the PLL setting has been changed to match the following settings.
 However, I can hear a fairly clear sound when I tested it with the EVM Default value below,
but when I hear the sound after changing the setting like above, I hear an unclear little dull sound.
Is it a problem to connect the bit clock pin directly to the master clock pin?
Or should I change the register settings for bit clock or master clock?
Please check it.
Thank you
Best regards
From Anthony
  • Hello Anthony,

    Our product expert is in another time zone and will get back with you in the next day.

  • Hi Anthony,

    We recommend to directly configure BCLK as input to PLL by setting B0_P0_R5:D5-D2 appropriately. It would avoid any potential issues with blue wiring.

    It would be better to try the highlighted configuration with PRB_P6 since it has the lowest resource requirement. Swapping MDAC and NDAC (i.e. MDAC = 5 and NDAC = 3) and MADC and NADC (MADC = 5 and NADC = 3) in the highlighted configuration would run the DSP at a higher clock rate and avoid issues related to insufficient MIPS.

    Best Regards

  • Hi 

    Thank you for your reply.

    But is not the left channel mode for PRB_P6? We need a stereo output. Can I still configure it with PRB_P6?

    Please check it.

    Thank you.

    Best Regards.

    From Anthony.

  • Hi Anthony,

    Please try the following for stereo configuration and let me know if you observe any issues:

    1. Use PRB_P1,

    2. change MDAC = 5, NDAC = 3, MADC = 5 and NADC = 3 in your clock tree to clock the DSP at higher speed, and

    3. set BCLK as PLL input.

    Best Regards.