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Part Number: PCM1864-Q1
My customer is using PCM1864 in slave mode and TDM mode with 2 Mics+2 Speakers single-end input.
Two things are really blocked their development process. Could you kindly help with these? Thank you！
1. When the VIN3P and VIN4P pins has no signal input, customer still receive some noise in the extract VIN3P and VIN4P data from DOUT.
What do you think may cause these noise in no input signal channel ?
We tested the noise in 4 conditions: only when ADC is muted, noise can disappear. Noise test result in the extract VIN3P and VIN4P data from DOUT is shown in following figures(In figures, result in green is dB, result in red is frequency waterfall).
1.1 Unmute ADC of VIN3P & VIN4P, configure VIN3P and VIN4P as schematic shows; Result: Large noise.
1.2 Unmute ADC of VIN3P & VIN4P, connect VIN3P and VIN4P pins to GND; Result: very little noise.
1.3 Unmute ADC of VIN3P & VIN4P, not connect anything to VIN3P and VIN4P pins; Result: very little noise.
1.4 Mute ADC of VIN3P & VIN4P, configure VIN3P and VIN4P as schematic shows; Result: No noise.
2. As following result shows, register 0x72~0x78 can show device DVDD and LRCLK error, but device can get DOUT. Is this an odd status?
Is this the reason that cause noise in the extract VIN3P and VIN4P data from DOUT?
For your reference, here is their schematic and their register configuration(according to TIDA-01454).
Slave & TDM Mode register
0x00 0x00 // Change to Page 0
0x01 0x20 // PGA CH1_L to 16dB
0x02 0x20 // PGA CH1_R to 16dB
0x03 0x20 // PGA CH2_L to 16dB
0x04 0x20 // PGA CH2_R to 16dB
0x05 0x87 // Enable SMOOTH PGA Change; Independent Link PGA; Enable Automatic Clipping Suppression
0x06 0x41 // Polarity: Normal, Channel: VINL1[SE]
0x07 0x41 // Polarity: Normal, Channel: VINR1[SE]
0x08 0x44 // Polarity: Normal, Channel: VINL3[SE]
0x09 0x44 // Polarity: Normal, Channel: VINR3[SE]
0x0A 0x00 // Secondary ADC Input: No Selection
0x0B 0xdf // RX WLEN: 16bit; TX WLEN: 16 bit; FMT: TDM format
0x0C 0x01 // 4CH TDM
0x10 0x00 // GPIO0_FUNC – GPIO0; GPIO0_POL - Normal
0x11 0x50 // GPIO3_FUNC - DOUT2; GPIO3_POL - Normal
0x12 0x00 // GPIO0_DIR - GPIO0 - Input
0x13 0x40 // GPIO3_DIR – GPIO3 – Output
0x20 0x61 // MST_MODE: Slave; No use for crystal, so set SCK_XI_SEL as SCK; CLKDET_EN: Enable
The problem that is being shown in the audio plots could potentially be related to the errors you are reading from the 0x72 and 0x78 registers. Could the customer please provide a little more information regarding those?
Can they check the DVDD output and share a scope capture of the voltage? Is there any excess noise on DVDD? Is it dropping below the recommended voltage?
For the LRCLOCK what is the rate they are using, the duty cycle, is it inverted? Could they share a scope capture of this with the frame sync as well?
Precision ADC Applications
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In reply to Scott Cummins:
Thanks for your reply!
1. For DVDD,I have 3 questions.
(1) Is it OK to confirm DVDD by testing DVDD Pin voltage? Because I did not find a DVDD output pin that you mentioned in your last reply.
(2) What else can cause this DVDD register status?
Because the customer tested DVDD pin voltage and it was a good 3.3V, but DVDD register 0x78 is still 0x03 and indicates DVDD bad.
(3) Can this bad DVDD device status cause the noise issue?
Because with a good 3.3V DVDD, the noise still exists , as following audio plot show.
2. For CLOCK, I have 2 questions.
(1) Is it necessary for BCLK to be 50% duty cycle?
Because I did not find requirement for BCLK duty cycle in datasheet, and the BCLK that customer used is not strictly 50% duty cycle. Will this cause noise as shown in audio plot?
(2) I noticed some registers indicate conflict device status as following. Will this cause the noise shown in audio plot?
The register 0x72 indicates device status is WAIT CLOCK STABLE, and register 0x75 indicates BCLK and LRCLK are both ERROR, but register 0x73~0x74 indicates the device has been applied a 16kHz LRCLK and a BCLK=256*LRCLK, it is conflict with device status that register 0x75 indicated.
3. For LRCLK, LRCLK rate is 16kHz, duty cycle is 1/256( T_LRCLK_high = 1BCK ), as shown in following scope capture.
In reply to Yunjing Wang1:
Yes, you can confirm the DVDD by checking the DVDD pin. I will have to get some help from design or systems to understand what other conditions can cause the DVDD status register to show bad or missing. Just to confirm again, the DVDD is a stable 3.3V with no noise on it? An unstable DVDD could certainly contribute to what is being seen here.
The BCLK does not necessarily need to be 50% duty cycle as long as the pulse duration high and pulse duration low specifications are met (tbckh and tbckl in the datasheet are both 1.5*tscki). I need to look into the other clock errors that you are seeing as well.
Out of curiosity has the customer tried using the LRCLK at 50% duty cycle instead of 1/256?
Thank you for your reply.
For DVDD, we can see 20mV peak-peak noise in DVDD3.3V pin, it's only 0.6% of 3.3V. Can this cause a BAD DVDD status?
After discussion, if there is any other conditions can cause BAD DVDD status?
For clock, I am asking customer to try 50% duty cycle. I will post a update of this when they complete it.
Thank you for you support.
Since there are two issues: DVDD bad and clock error, we are debugging these two issues one by one.
Here is an update about DVDD issue.We configure PCM1864Q1 as master mode, use clocks from crystal rather than customer's SoC. Register configuration is same as EVM master mode.
Based on recent debug and test, I want to ask 2 question.
1. Is it OK to use same GND net in DGND pin and AGND pin for PCM1864Q1? If ok, is there any isolation between AGND and DGND inside PCM1864Q1 ?
Because I noticed customer is using a same GND net in DGND pin and AGND pin, which is the same as EVM schematic.
2.Is it possible that the value of 0x78 register latched on 0x03 then cause a permanent DVDD status error?
Because we find that we still readout a DVDD BAD status from Reg 0x78, with a standard DC source to supply 3.3V (Noise in 3.3V supply is quite small, as following picture shows).
BTW, EVM works well with same register configuration but customer's PCB does not.
Look forward to your answer. Thank you!
For PCM1864Q1 issue about DVDD register bad status, now we find the direct thing caused DVDD bad status.
DVDD register(0x78) shows DVDD BAD only when IOVDD and LDO pins are connected to external 1.8V supply. Can you help explain the reason and the solution?
Here is the test results.
1.When customer connected IOVDD to 3.3V and without external 1.8V LDO supply, DVDD register shows good status.
2. When connect IOVDD to 1.8V and use an external 1.8V LDO supply, DVDD register always shows bad status.
3. These 1~2 results indicate an external 1.8V LDO will cause a bad DVDD register status.
4. But customer have tested external 1.8V supply, the noise of external 1.8V supply is about 20mV. I have send you the scope picture of 1.8V supply.
Then why external 1.8V supply to IOVDD and LDO pin can cause a bad DVDD status?
For your reference, below pictures are their schematic, external 1.8V supply to IOVDD pin and LDO pin comes from LP5912-1.8.
Thank you for the additional information and the schematic. I will be taking a look at this and I will get back to you this week.
Do you find any solutions or reasons for above question: DVDD bad status when connect LDO pin to an external 1.8V supply?
We have captured a waveform of the external 1.8V supply, as follow picture shows, it's a low noise supply, about 20mVpp noise.
Thank you & Best regards.
The 1.8V supply does look like it should be sufficient for the PCM1864. And as long as the LDO and IOVDD pins are supplied from the same 1.8V supply then this should work as expected. It also seems that the BCLK is running at a rate low enough for the external 1.8V supply to be used, as the limit is 25Mhz, and they are running at around 4Mz. Is there any way that they can try adjusting and lowering the BLCK rate to see if this affects the DVDD good status when using an external LDO and IOVDD supply?
I will let customer try to lowering BCLK rate.
Can you explain how the BCLK rate affect LDO and IOVDD supply? And what's the maximum BCLK rate to avoid this effect, because 4MHz BCLK is already much lower than 25MHz limit.
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