Other Parts Discussed in Thread: PCM1864, TIDA-01454
Dear team,
My customer is using PCM1864 in slave mode and TDM mode with 2 Mics+2 Speakers single-end input.
Two things are really blocked their development process. Could you kindly help with these? Thank you!
1. When the VIN3P and VIN4P pins has no signal input, customer still receive some noise in the extract VIN3P and VIN4P data from DOUT.
What do you think may cause these noise in no input signal channel ?
We tested the noise in 4 conditions: only when ADC is muted, noise can disappear. Noise test result in the extract VIN3P and VIN4P data from DOUT is shown in following figures(In figures, result in green is dB, result in red is frequency waterfall).
1.1 Unmute ADC of VIN3P & VIN4P, configure VIN3P and VIN4P as schematic shows; Result: Large noise.
1.2 Unmute ADC of VIN3P & VIN4P, connect VIN3P and VIN4P pins to GND; Result: very little noise.
1.3 Unmute ADC of VIN3P & VIN4P, not connect anything to VIN3P and VIN4P pins; Result: very little noise.
1.4 Mute ADC of VIN3P & VIN4P, configure VIN3P and VIN4P as schematic shows; Result: No noise.
2. As following result shows, register 0x72~0x78 can show device DVDD and LRCLK error, but device can get DOUT. Is this an odd status?
Is this the reason that cause noise in the extract VIN3P and VIN4P data from DOUT?
For your reference, here is their schematic and their register configuration(according to TIDA-01454).
Slave & TDM Mode register
Reg Value
0x00 0x00 // Change to Page 0
0x01 0x20 // PGA CH1_L to 16dB
0x02 0x20 // PGA CH1_R to 16dB
0x03 0x20 // PGA CH2_L to 16dB
0x04 0x20 // PGA CH2_R to 16dB
0x05 0x87 // Enable SMOOTH PGA Change; Independent Link PGA; Enable Automatic Clipping Suppression
0x06 0x41 // Polarity: Normal, Channel: VINL1[SE]
0x07 0x41 // Polarity: Normal, Channel: VINR1[SE]
0x08 0x44 // Polarity: Normal, Channel: VINL3[SE]
0x09 0x44 // Polarity: Normal, Channel: VINR3[SE]
0x0A 0x00 // Secondary ADC Input: No Selection
0x0B 0xdf // RX WLEN: 16bit; TX WLEN: 16 bit; FMT: TDM format
0x0C 0x01 // 4CH TDM
0x10 0x00 // GPIO0_FUNC – GPIO0; GPIO0_POL - Normal
0x11 0x50 // GPIO3_FUNC - DOUT2; GPIO3_POL - Normal
0x12 0x00 // GPIO0_DIR - GPIO0 - Input
0x13 0x40 // GPIO3_DIR – GPIO3 – Output
0x20 0x61 // MST_MODE: Slave; No use for crystal, so set SCK_XI_SEL as SCK; CLKDET_EN: Enable