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SRC4382: AES output pin has Noise floor sputtering and carrier appears to be 'slipping'

Jaye Waas
Intellectual 525 points
Part Number: SRC4382

On the AES output pin 34,  the carrier is slipping and at the same time the down-stream result is low level audible noise, much like pink noise bursts. 

This occurs with or without an AES input to the SRC4382.

The master clocking and power supply voltages appear stable.

What may be happening to have this result?

Jaye

  • 0
    TI__Mastermind 30030 points

    Jaye, 

    Can you share your register configuration and relevant information about the digital audio bus?

    best regards

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    Intellectual 525 points

    Here are the register settings;

    InitAES[CS4382NUMENTRIES]=

    {

                   {              0x7f, 0x00           },

                   {              0x03, 0x31          },

                   {              0x04, 0x03          },            // Register 04 : 0x03 (Port A Control2)

                   {              0x05, 0x31          },

                   {              0x06, 0x03          },            // Register 06 : Port B Control2

                   {              0x07, 0x68          },            // Register 07 : Transmitter control1

                   {              0x08, 0x00          },            // Register 08 : Transmitter control2

                   {              0x09, 0x00          },            // Register 09 : Transmitter control3

                   {              0x0B, 0x33          },            // Enable Interrupts

                   {              0x0C, 0xAA          },            // Set Interrupts to Level Trigger

                   {              0x0D, 0x08          },            // Register 0D : Receiver control1

                   {              0x0E, 0x18          },            // Register 0E : Receiver control2

                   {              0x0F, 0x22           },            // Register 0F : PLL1 Configuration 1, Receiver PLL1,24Mhz

                   {              0x10, 0x00          },            // Register 10 : PLL1 Configuration 2

                   {              0x11, 0x00          },            // Register 11 : PLL1 Configuration 3

                   {              0x16, 0xFF           },            // Enable Interrupts

                   {              0x17, 0x01          },            // Enable Interrupts                                                                                                  

                   {              0x18, 0xAA          },            // Set Interrupts to Level Trigger

                   {              0x19, 0xAA          },            // Set Interrupts to Level Trigger

                   {              0x1A, 0x02          },            // Set Interrupts to Level Trigger

                   {              0x2D, 0x42          },            // Register 2D : 0x42 (SRC control1)

                   {              0x2E, 0x00          },            // Register 2E : 0x00 (SRC control2)

                   {              0x2F, 0x00           },            // Register 2F : 0x00 (SRC control3)                            

                   {              0x01, 0x3F           }              // Register 01 : 0x3F (Power up the dir block)

    };

     

    InitAnalog[CS4382NUMENTRIES]               =

    {

                   {              0x7f, 0x00           },

                   {              0x03, 0x01 },

                   {              0x04, 0x03          },            // Register 04 : Port A Control2

                   {              0x05, 0x11},                        

                   {              0x06, 0x03          },            // Register 06 : Port B Control2

                   {              0x07, 0x68          },            // Register 07 : Transmitter control1

                   {              0x08, 0x00          },            // Register 08 : Transmitter control2

                   {              0x09, 0x00          },            // Register 09 : Transmitter control3

                   {              0x0B, 0x33          },            // Enable Interrupts

                   {              0x0C, 0xAA          },            // Set Interrupts to Level Trigger

                   {              0x0D, 0x18          },            // Register 0D : Receiver control1

                   {              0x0E, 0x00          },            // Register 0E : Receiver control2

                   {              0x0F, 0x22           },            // Register 0F : PLL1 Configuration 1, Receiver PLL1,24Mhz

                   {              0x10, 0x00          },            // Register 10 : PLL1 Configuration 2

                   {              0x11, 0x00          },            // Register 11 : PLL1 Configuration 3

                   {              0x16, 0xFF           },            // Enable Interrupts

                   {              0x17, 0x01          },            // Enable Interrupts                                                                                                  

                   {              0x18, 0xAA          },            // Set Interrupts to Level Trigger

                   {              0x19, 0xAA          },            // Set Interrupts to Level Trigger

                   {              0x1A, 0x02          },            // Set Interrupts to Level Trigger

                   {              0x2D, 0x40          },            // Register 2D : 0x42 (SRC control1)                

                   {              0x2E, 0x00          },            // Register 2E : 0x00 (SRC control2)

                   {              0x2F, 0x00           },            // Register 2F : 0x00 (SRC control3)                            

                   {              0x01, 0x3F           }              // Register 01 : 0x3F (Power up the dir block)

    };

  • 0 in reply to Jaye Waas
    Intellectual 525 points

    What is required for me to do so I can receive some sort of an answer to my question?

    I provided the register settings.  I had hoped someone who is supposed to support the SRC 4382  would review them and comment on any possible related cause that might explain the noise output from the SRC.

    Please let me know.

    thank you.

    Jaye

  • 0 in reply to Jaye Waas
    TI__Mastermind 30030 points

    Hi Jaye, 

    Your configuration mentions that you are setting PLL1 using 24Mhz,  but then you set it up for the values for 24.5760Mhz, Is your clock 24Mhz or 24.5760MHz? 

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    Intellectual 525 points

    I am using 24.576 MHz.

    Jaye

  • 0 in reply to Jaye Waas
    TI__Mastermind 30030 points

    Jaye, 

    I'm not seeing any configuration that explains the sputtering. is this happening on multiple devices?  are you using an EVM or your own board?

    best regards,

    -Steve Wilson

  • 0 in reply to Steve-Wilson
    Intellectual 525 points

    I am using our own boards.  This is present on at least 3 different circuit board designs, all similar in concept.  For instance the SRC follows a Dante Digital audio interface in one board and in another it follows an audio DSP  and in the third it follows hardware mux selected sources.

    My diagnostics show that insertion of AES sourced from Audio Precision system 525 into the output path of the SRC results in 'no slipping detected' and no audible sputtering.

    Using the SRC AES output shows 'slipping' ans audible sputtering.

    A limited test by another engineer was to replace the SRC chip and the reported result is no audible sputtering. The slipping test was not run. I will ask for that test today.  .

    Jaye