Part Number: TAS2505-Q1
Due to MCU limitation, we do not have general audio sampling rate, such as 8k, 16k, 48kHz. Currently, we have 10k, 25k and 50kHz options. Below is the application circuit:
I have tested another media source with the same configuration but 48kHz sampling, it works. Then, I modified the clock setting to fit TAS2501-Q1 requirement. My setting is as below:
For more detail, please refer to attached config file.PGWW20_ClassD_playback_FS25k.cfg
However, I hear the high frequency tone, not 1kHz tone. What I would like to confirm are
I would like to attach the pcm raw data, but it seems not work. If you are interesting in, please let me know. I could send it by email.
- 1kHz tone, -10dBFS, 0.5s
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In reply to Nick Hsiao19:
You shouldn't have issues with your configuration. I tested it with the help of our TAS2505-Q1EVM and it works correctly. I can get a correct sine wave. I also tested a different configuration with our suggested PLL values and it works fine too.
Is your data in 2's complement signed PCM format?
Do you have an Audio Precision tool to test the sine wave data from an I2S transmitter?
Best regards,Luis Fernando Rodríguez S.
In reply to Luis Fernando Rodriguez S.:
I noticed that the PCM raw data format is LSB,MSB. We transferred to MSB,LSB, then it works, both output voltage and frequency are correct. But I found below issue that at the end of I2S, we will stop the BCLK along with data, it seems the digital processing of TAS2505 stop at the meanwhile, so the waveform stop at a certain voltage. (yellow is WS, and red is AMP output with LC filter)
I tried add 0 data to keep BCLK for extra 1ms, the issue is gone. So my question are, is it reasonable that DAC stops when BCLK stops? if yes, how much the duration I have to keep BCLK working?
I looked your setting, some questions about it
(1) Page 1, register 2, D2: Reserved. Don't write any value other than Reset Value.(reset=1)# Page Switch to Page 1 W 30 00 01# LDO output programmed as 1.8V and Level shifters powered up.W 30 02 00
(2) Page 0, register 63, D2-D3 is reserved, Write only default values. (default=01)# Only LDAC powered up.Dac path setup LDAC data Mono of LDAC and RDAC. RDAC data disabled.Soft step 1 per Fs.W 30 3f B0
Are the above two questions typo or there are new definition?
The BCLK and the DAC processing blocks are always associated for the beginning and the end of the internal activity. Generally, the processing blocks require of at least 8 BCLK pulses in order to start its digital processing. Similarly, these blocks require of around 8 BCLK pulses to finish its activity.
Regarding the settings that I shared, these are the settings that we use as initialization code for our TAS2505-Q1EVM. You may use your current settings if these code lines don't apply to your configuration.
Got it. You really help me a lot.
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