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[TAS880021ADCAR] Logic verification on TDM Interface

changyong Heo
Prodigy 30 points

Hello, sir

I'm a logic design engineer working for DTV SoC and now considering designing logic for TDM type audio signal interface.
It looks not such complex interface conceptually but still I need to verify my design work well with TI AMP device.
One of my customer will use TI's AMP IC, TAS880021ADCAR.

Unfortunately, we have a reason not for using FPGA system to verify interface logic in advance.
Therefore, I think the only way to verify my logic is to use HDL simulation model.
Actually, I've experienced at designing more common audio interface like I2S, spdif but TDM is very new to me.
Currently, I couldn't confirm if my design really works well with AMP IC.

So, Could you please inform me of a way to use kind of ASIC simulation model for receiver which has TDM interface that supports for AMP IC ?
We use verilog language for HDL design.

I'm looking for TDM RX simulation model in verilog and relevant test bench's.

Thanks in advance

russel Heo.

  • 0
    TI__Expert 6295 points

    Hello Russel Heo,

       as this is one custom release device and we don't have specific HDL simulation model ready. as this device already RTM, are you good to apply EVM and do board level evaluation? who is your end customer?

    Regards

    Linda

  • 0 in reply to Xiaolin Qin
    Prodigy 30 points

    Hello Linda

    My end customer is also another division in samsung.

    As I mentioned, I couldn't use any kind of fpga device for the time being.

    We have no EVM board that has fpga device.

    I'm thinking the only way to check my design might be logic simulation in HDL now.

    I think the HDL simulation model don't have to be identical to the device they are going to use.

    It'll be OK if it has the known TDM interface of audio signal.

    Thanks

    russel Heo.

  • 0 in reply to changyong Heo
    TI__Expert 6720 points

    Hi Russel Heo,

    As Linda mentioned, it's very hard for us to provide TDM HDL for customer. The behavior is verified through real silicon EVM board.

    Even it might be difficult with current situation, it's still the only way to verify your design with FPGA + EVM board.

    Regards,

    Matthew

  • 0 in reply to Matthew Miao
    Prodigy 30 points

    Hello, Matthew.

    Thanks for the update.

    Yes, I know the best way to verify logic is using my design with FPGA + EVM board.

    And also, I understand you couldn't give me a TDM HDL.

    I'm just wondering whether I can get the behavioural simulation model of TDM module, not real HDL from you or somewhere in public domain.

    Regards,

    Russel.

  • 0 in reply to changyong Heo
    TI__Genius 13970 points

    Hello Russel,

    We don't have specific public behavioral models of the TDM module that we can provide.

    Best Regards,

    Luis