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Part Number: TLV320AIC3268
We are testing DIGITAL(I2S) TO DIGITAL(I2S) MIX using two TLV320AIC3268 EVMs.
If we set PLL CLK = MCLK and MCLK = 11.3MHZ in EVM's DEFAULT setting, the audio quality will sound very good.However, I changed the PLL CLK = MCLK, MCLK = 2.82Mhz, and changed the PLL settings as shown in the table below in the datasheet.
However, the resolution of the audio quality is lower than that of 11.3Mhz.Does the higher the frequency of the PLL CLK, the better the sound quality?
No, The frequency of the PLL input should not have any effect on the sound quality. When you say the sound quality is lower, do you have some measurements to show that the sound quality is lower?
Also confirm your settings, and make sure that you have it programmed correctly in both cases. You could also share the two configurations that you used and I could see if I could see what was going on.
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In reply to Steve-Wilson:
Unfortunately, due to time and equipment conditions, we do not have comparable data for sound quality.
But it's clear that it's a big difference.
Of course, my settings may be wrong.
So we share about PLL Clokc configuration.
In reply to Anthony Yoo68:
Please check it.
for the 11.289Mhz PLL_IN clock settings your MADC is set to 8, making the DSP clock 45.12Mhz, while the other has the MADC set to 3. making the DSP clock = 16.92Mhz. The issue could be related to the processing requirements of the processing block. ie the processing block needs more DSP cycles than the Current clock allows for.
Try swapping the NADC/MADC settings in the PLL_IN = 2.82Mhz. So that MADC = 5 and NADC = 3. This would give you a DSP CLOCK of 28.2Mhz.
That will give you more DSP cycles. While the DSP clock rates are still not identical, I think the increase should resolve the issue.
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