TAS2505-Q1: Power supply timing

Narikazu-san,

My colleague will take a look at this E2E thread and will answer as soon as possible.

Best regards,
Luis Fernando Rodríguez S.

Narikazu-san, 

For your first question, I think you are asking about the voltage level of each power supply voltage. If so, then you are correct. 

For your second question, it is not necessary to power down in reverse, the external supplies can just be turned off completely. If the 1.8V rail cannot be turned off, the PLL and HP level shifters must be powered down (Page 1, Register 2, D3=1), the LDO bandgap must be powered down (Page 1, Register 1, D1=1), power down the POR circuit (Page 1, register 1, D4=0). This state results in a device shutdown current < 1.5uA. 

Hi,

Thank you for your answer.

<About Question 1>
OK.
I understand that if 3.3V, 10% of 0.33V and 90% of 2.97V specify the timing of the power-up sequence.
No problems?

<About Question 2>
I understood that the power can be turned off at any time.
However, we decided that it would be safer to turn off 1.8V first, so we are planning to design with the following power-off sequence.

We are considering using IOVDD 3.3V, AVDD and DVDD 1.8V, and SPKVDD 4.2V.
The power-off sequence is designed in the order of 1.8V → 3.3V & 4.2V.
When 1.8V is 20% of 0.36V, 3.3V & 4.2V fall start.
No problems?

Please answer whether there is no problem in understanding and designing each question.

Thanks and best regards,

Narikazu