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TAS2557: Power down and mute / Low power sleep

Part Number: TAS2557

Hello!

I am using TAS2557 working as a master on I2S (WCLK 44.1kHz, BCLK 1.4MHz ,16bit) in ROM Mode 1.
My TAS2557 is a part of an embedded system running on a 1.5V battery, so naturally i want the TAS2557 to consume as little power as possible while not playing audio. So, when there is no audio to be played (i know this in my program) i want to put the TAS2557 in "Low power sleep mode" or use a "power down and mute" sequence. And when there is audio to play, i want to wake up the device again.

Whenever i try to write the example presented in the datasheet, the clocks generated by TAS2557 (WCLK and BCLK) shuts down and the power consumption is significally lowered. But whenever I try to power up the device again, nothing is happening. 

So my question is: What sequence of commands do i need to send in order to get the device to power down and power up somewhat quick? I dont want to re-initialize the device all over again.
I don't necessarily need the absolute lowest power consumption possible. The time it takes to power down/power up is more important.

Thank you in advance,
/Viktor

  • Hi Viktor,

    I'll take a look at your questions and provide further comments soon.

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuators

  • Viktor,

    I assume you're using 9.5.3 to sleep and 9.5.2 to power up, correct?

    For sleep, it is correct to use the script from data sheet section 9.5.3, this will put the device into sleep mode disabling several internal blocks.

    Regarding power up, some changes are needed on 9.5.2 script:

    • If you don't want to fully reinitialize the device, you can remove the SW reset command. If you keep this command, the whole device will go back to default state.
    • If you're using PLL (I assume you do since you're using the device as Master derived from MCLK), you must power it up during the startup sequence, the script from the datasheet does not include PLL.
    • Since clock dividers and PLL were powered down for sleep mode, you need to reinitialize their values based on your configuration.

    Attached are some scripts I used on my setup. You can use them as reference. I use MCLK = 12.288MHz and device is Master generating BCLK = 3.072MHz and WCLK = 48kHz

    Best regards,
    -Ivan Salazar
    Applications Engineer - Low Power Audio & Actuator

    48k_12.288M_ROM1_Master.cfg

    powerup.cfg

    sleep.cfg