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TAS2505: DAC_fs and I2S sample frequency

Maciej Lasota
Prodigy 170 points
Part Number: TAS2505

Hello,

I have question regarding ADC_fs in TAS2505. Clock distribution tree from "Reference guide" is shown below:

There are many settings having influence over DAC_fs: R, J, D, P in the PLL and additionally NDAC, MDAC, DOSR.

My question is if the DAC_fs must be equal or be integer multiplication (or division) of the sample rate (WCLK) on the I2S input?

I use TAS2505EVM evalboard and noticed there is not possible to change I2S WCLK on that board. It is fixed on 48kHz regardless of sample rate of the audio file being played from PC. Probably the streaming controller (TAS1020) on that board takes care to provide such frequency and it is not possible to change it.

When playing with digital settings in the TAS2505EVM GUI I can set different DAC_fs values (having constant WCLK 48kHz) and these changes in DAC_fs have big influence over sound quality. In the device where I use TAS2505 I can set different sample frequency (WCLK). I do not use MCLK as DAC clock source, but BCLK with the PLL. So I guess I need to choose correct I2S sample rate and DAC_fs to get optimal sound quality, but I don't know answer to the question I have asked above.

Thank you and best regards / Maciej

  • 0
    TI__Guru* 84915 points

    Hi, Maciej,

    Welcome to E2E and thank you for your interest in our products!

    Our team will take a look at this. We will answer as soon as possible.

    Thank you.

    Best regards,
    Luis Fernando Rodríguez S.

  • 0
    TI__Genius 17467 points

    Hello Maciej, 

    The DAC_fs should be an integer multiplication/division of WCLK. In master mode, WCLK=DAC_fs. 

    DAC_fs ranges from 8kHz to 192kHz. 

    Please let me know if you have any additional questions. 

    Best Regards, 

    Carolina 

  • 0 in reply to Caro Walter
    Prodigy 170 points

    Thank you Carolina!

    We use TAS2505 in slave mode (microcontroller provides BCLK and WCLK; we use BCLK as PLL_CLKIN). Currently we have 44.1 kHz audio frequency (WCLK) configured in microcontroller. We use 16-bit words on I2S, so it gives BCLK = 44.1 x 2 x 16 = 1411.2 kHz

    PLL_J = 4; PLL_D = 0; PLL_P = 1; PLL_R = 2, so the PLL_CLK = BCLK x 8. We have NDAC = 4; MDAC = 2; DOSR = 128. So, the final division ratio is PLL_CLKIN/128 => DAC_fs = 1411.2 kHz / 128 = 11.025 kHz.

    So DAC_fs is integer division (4x lower) of WCLK and the sound seems to have good quality. That's fine but I am a bit surprised that having such low DAC_fs gives good sound quality. Do you know how the DAC_fs influences sound quality? Is it desirable to have it equal or higher than WCLK, or it does not matter as long as their ratio is integer?

    Best regards / Maciej

  • 0 in reply to Maciej Lasota
    TI__Genius 17467 points

    Hello Maciej, 

    The application reference guide in section 2.4 states: "The high oversampling ratio (normally DOSR is between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise generated within the delta-sigma modulator stays outside of the audio frequency band."

    In this case, DOSR =128, therefore the ratio for oversampling within the delta-sigma modulator is at its highest. This allows the DAC to provide good performance at a lower sampling rate. 

    We have seen issues in the past when there is a non-integer relation between WCLK and DAC_fs. 

    All the best,

    Carolina