Part Number: TAS2505
What is recommended setting of "PLL clock range" bit (Page 0; Register 4; D6) in TAS2505?
I have found some description in the slau472 TAS2505 Reference Guide, but it is described for TLV320AIC3256, so I am a bit confused:
Are above settings valid also for TAS2505?
How important is this setting? I see that ranges of frequency recommended for using with 0 or 1 have huge range of overlap, so I guess it is not critical setting...
Thank you and best regards / Maciej
The PLL Description found in Section 22.214.171.124 of the Application Reference Guide is for the TAS2505 not TLV320AIC3256. Thank you for catching this, we will fix it in a later revision of the reference guide.
As for choosing which "PLL Mode" Page 0, Reg 4, D6 it depends on how low your AVDD is and how low the output clock is. It is meant to accommodate if you have lower range.
Therefore, if your AVDD is >1.65 V and have a PLL_CLK frequency that falls within 90 to 130 MHz, a "High PLL Clock Range" is chosen and Page 0, Reg 4, D6 = '1'.
Please let me know if you have any further questions.
All the best,
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In reply to Caro Gomez:
Thank you for your answer!
We have AVDD = 1.8V, but PLL_CLK is much lower than the ranges described in the table. We use BCLK with 1.408MHz as PLL input. We have PLL_R = 2 and PLL_J = 4 which gives multiplier x8. So our PLL_CLK is 1.408 x 8 = 11.264MHz and it is much below the Min PLL_CLK (75 MHz).
Can we stay with 11.264MHz (what value of PLL mode bit should be set then?), or should we increase PLL multipliers to be in the range 75 - 140MHz or 90 - 150MHz?
All best / Maciej
In reply to Maciej Lasota:
I would change the multipliers to fall within the min and max clock frequencies for PLL_CLK.
All the best,
Thank you Carolina!
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