Other Parts Discussed in Thread: TLV320AIC3256
Hello,
What is recommended setting of "PLL clock range" bit (Page 0; Register 4; D6) in TAS2505?
I have found some description in the slau472 TAS2505 Reference Guide, but it is described for TLV320AIC3256, so I am a bit confused:
Are above settings valid also for TAS2505?
How important is this setting? I see that ranges of frequency recommended for using with 0 or 1 have huge range of overlap, so I guess it is not critical setting...
Thank you and best regards / Maciej