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PCM1794: PCM1794 relation between Clock accuracy and output accuracy

louie li
Prodigy 170 points
Part Number: PCM1794
Other Parts Discussed in Thread: SRC4392

Dear engineer,

We decide to develop a HIFI DAC with PCM1794 but meet some theoretical problem.

It is easy to provide PCM1794 with an accurate SystemClock, frequency of which is more than100 times larger than clock of I2S.

But clock accuracy of I2S is unstable. e.x sometimes time length of high-voltage signal is shorter (maybe 1or2 clock cycle of SysClock). if I2S interface input a "1010"digital signal, but the length of both 1 are 127SysClock cycle while the length of both 0 are 129SysClock cycle, will PCM1794 correct the jitter to be ideal signal which are all 128SysClock cycle long?

If such Jitter of I2S signal cannot be corrected by PCM1794, is there any suggested method to Reorganise clock of I2S signal?

Thank you!

  • 0
    TI__Guru 52683 points

    Hi Louie,

    This depends on which I2S clocks are unreliable.  The LRCK and SCLK should be based on the same master clock. These two clocks are the most critical.  If you, for example, had 63 SCLK periods instead of 64 for multiple LRCK periods, the two would be out of sync, resulting in the PCM to halt playback and resynchronize.  

    The BCK is less critical - as long as all data bits on transmitted in the LRCK period.  

    If you do not think you can achieve this, then I recommend you use a sample rate converter device to resynchronize your data - consider the SRC4392.

    Thanks,

    Paul