• Resolved

TLV320ADC3100: AOSR and ADC Digital Filter Engine Decimation

Intellectual 1155 points

Replies: 3

Views: 53

Part Number: TLV320ADC3100

Hi Team,

We are quite new to this device and we need some clarifications regarding the Register 22 (ADC Digital Filter Engine Decimation). My understanding was that the digital decimation was set by AOSR (the oversampling ratio). How is this register different from that? Is it mainly for the CIC conditions?

Thanks in advance for your help.

Kind Regards,

Jejomar

  • Jejomar, 

    I don't believe that these are necessary to set if you are using the Preset processing blocks.  If you are using the MiniDSP,  there were only 2 frameworks ever created,  2x and 4x.  I will have to check in with the Design team on the reason for providing up to 16x decimation ratio when the tools don't provide support for it. 

    I will check in with them and get back to you by weeks end.  

    best regards,

    -Steve wilson

  • In reply to Steve-Wilson:

    Hello Steve,

    Thank you for the clarifications. Yes, our customer indeed tends to utilize the processing blocks.

    We look forward to hearing the design team's inputs for added reference.

    Kind Regards,

    Jejomar

  • In reply to Jejomar Iidefonso:

    Jejomar, 

    So If the customer is utilizing the preset processing blocks,  these registers are not used.  they can ignore them. 

    When using the programmable MiniDSP,  PPS only supports 2x and 4x decimation ratios.  This is all handled by PPS depending on the framework that is selected, and the customer does not need to manually set them. 

    best regards,

    -Steve Wilson