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TLV320AIC3106: ADC Offset / dynamic loss

Prodigy 20 points

Replies: 4

Views: 63

Part Number: TLV320AIC3106

Hi all.

I am currently using a TLVAIC3106 and I measure a digital offset added by the ADC even though input common mode voltage is at 1.35V.

Using the register 12 (set to 0x40 to enable high pass filter) this digital offset is removed.

My question is : as an offset reduces the input analog dynamic range, will the high pass filter allow to regain this loss ?

e.g. :

case 1.

Given all gain are at 0dB :

0.35V = 0x800000

1.35V => 0x000000

2.35V => 0x7FFFFF

case 2.

Given an offset of 0x003000:

0.35V = 0x803000

1.35V = 0x003000

2.3X (< 2.35V) = 0x7FFFFF

If  the high pass filter is applied to case 2, will it allow to achieve desired functioning (as in case 1) ?

Thank you.

  • Corentin, 

    The high pass filter will remove the DC offset from the digital audio.

    Regarding your dynamic range,  there is also a typical gain error of 0.8dB, which would mean that a .6448Vrms signal would be amplified by the PGA and ADC driver to create a  0.707Vrms input to the ADC. 

    best regards,

    -STeve Wilson

  • In reply to Steve-Wilson:

    Because the high-pass filter is after the ADC in the digital path, the ADC input stage will still saturate asymmetrically due to the offset error as you suspected in Case 2.

    This is in addition to the gain errors Steve mentioned.

    Collin Wells
    Precision ADC Applications

  • In reply to Collin Wells:

    Hi !

    Thank you for your answers.

    What is surprising to me is that we did some measures, and we noticed that the HP filter allows to regain the dynamic.

    Here is our experiment (we have an analog path which add some gain) :

    When no signal is applied, we have measured a digital offset which is equivalent to a 200mVRMS input signal.

    Without the filter, the ADC saturates with a 1.6VRMS sinus at 1KHz.

    After the activation of the digital HP filter, we noticed that there were no more saturation at 1.6VRMS neither at 1.7VRMS but at 1.8VRM (here are our 200mVRMS).

    I agree that it is unexpected as the filter is placed after de ADC.

    I then have two questions which result to this offset issue :

    1. Is there a guaranteed range value for the offset for the AIC3106 ?

    2. If not, is there a reference of device for which TI can guarantee the ADC offset within a certain range ?

    Best regards.


  • In reply to Corentin NICOLAS:


    It isn't common for TI to provide DC specs for audio ADCs,  that being said the offset is admittedly higher on this device than on our later codec offerings.  for example the AIC3204 would not have as large an offset, or gain error. 

    It would be uncommon to spec a MAX for this kind of spec as well. a typical value would be more expected.

    For the PCM3060 we do spec bipolar zero error with a max of 2% of FSR for Single ended,  but that is the only device I have seen with any kind of spec. 

    best regards,

    -Steve Wilson