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WEBENCH® Tools/LMK03328: Clock and Timing
Part Number: LMK03328
Tool/software: WEBENCH® Design Tools
Hi Zoe and technical support team
I have related question about following E2E.
I tried Zoe's .mac(changed .pdf) you have adjusted RMS jitter with LMK03328EVM.
My waveform is below and red circle is peak to peak jitter(16.19ps).
When you tried it , RMS jitter shows 156.864fsec(peak to peak jitter 1.167ps(156.864x7.44). It is lower than my result.
【My environment 】
Power supply: Metronix 545c(old product) → 5V for J3pin.
OUT7P/N → 100Ω for R75 . I probe on R75.
External Cap for Loop filter → 0.003uF for fraction
To design your own Clock Tree solution, visit WEBENCH Clock ArchitectMore information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html
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In reply to Timothy T:
Thank you for your reply.
I'd like to try your advice.
Keysite : DSAZ204A
→ I used TIE function of oscilloscope.
See attached URL , page 9.
How do you connect SMA cable between EVM and oscilloscope?
Do you connect two SMA of EVM to 2ch of Oscilloscope and calculate differential range on software of Oscilloscope?
Video of LMK03328EVM show that something change from differential to single .
Does it trans? Could you show product number of that?
By the way, I designed my board and it doesn't have SMA connector.
So I use differential probe to check jitter.
If you have any important point , could you share it?
DDR4's spec is very strict below. It specified 10ps p2p (BER 10-12)
So RMS jitter(st div) x 14.069 = peak to peak jitter.
TI's evaluation result, RMS jitter shows 156.864fsec for 266.625MHz.
So RJpk-pk = 156.864 fsec x 14.069 =2.2ps
It seems to be satisfied with DDR4 spec of 10ps (p2p).
In reply to ttd:
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