This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Part Number: CDCI6214
Hi,I am currently trying to configure the CDCI6214 to be implemented in future projects. Even though I did read the given data sheet (rev.B) and forum posts I cant solve my problem.I successfully programmed the device via I2C to produce a bypass-signal through output Y0. But I cant get a output signal on any other output channel. I already tried various different combination.A STM32 Nucleo L452RE is used for the I2C connection. I am leaving the EEPROMSEL and REFSEL pin floating while selecting the REF-Input via ref_mux. As a input signal I am using a 25Mhz square-wave which is generated with a Arbitrary Generator.I am using the GPIO1-Pin to check the PLL-lock. Even though I used the values from Table2. (first row) and settings from Figure33. I cant get the PLL to lock.
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Timothy T:
In reply to Maximilian Rentschler:
thank your for your help. I tried the registers you sent to me but i still cant get an output signal.
I'm starting to think that there may be some trouble with my test-setup because you said that this register map should run properly. Since I am not using the Evaluation Module but just the chip soldered on a breakout board this could be the only problem left.
I sent you a picture of the input signal. Its a 50Mhz signal from a SigGen. If you have no further explanation what could cause my problem I will wait till the first prototypes of the project board will arrive to test in on there directly.
Thank you anyway
Maximilian RentschlerAs a input signal I am using a 25Mhz square-wave which is generated with a Arbitrary Generator.
This was from above...
Maximilian RentschlerI sent you a picture of the input signal. Its a 50Mhz signal from a SigGen.
The prior registers I sent assume 25 MHz input. If you are using 50 MHz input, then this could be an issue.
I would boil the troubleshooting down to 4 items.
1) Ensure you are indeed programming the device.
If it ever got programmed into a mode where I2C was ignored, the way to get out of this is power up with EEPROMSEL and REFSEL floating and RESETN/SYNC at VDDREF level. Sounds like you're probably already doing that, but be sure the RESETN is high.
Maximilian RentschlerI am leaving the EEPROMSEL and REFSEL pin floating while selecting the REF-Input via ref_mux
2) A valid input & input configuration
As for the signal itself, it does appear to meet the requirements for a CMOS in terms of it's amplitude being from ~0 V to ~3.3 V. Provided you can see the input on Y0, everything should be good. You might consider testing with ip_byp_mux = 0 for output of REF direct. If you have a frequency counter synced to your sig gen, this would be the most accurate way to ensure CDCI6214 is getting your input signal properly.
If any trouble, I would try the AC-differential mode with a smaller swing, ~1.5 Vpp. Even if you can only provide it to the single input for test purposes.
Once all inputs considerations are covered, just be sure the output terminations are configured correctly. For example on our EVM, I had to change to a non-HCSL output to see the clock.
3) State of the PLL lock.
You are observing this on the output pin. You should still be able to get outputs even if it is not locked. You may need to set cal_mute = 0 to get those outputs.
A useful method to troubleshoot PLL lock failure is to look at debugging outputs of CLK_PFD_REF (from input) & CLK_PFD_FB (from VCO). These signals when output from two status pins should be phased locked with respect to one another. If you're not locked, these outputs should give you clues as to why not.. for example if one frequency is slightly higher or lower, or if a clock isn't present at all.
* Set GPIO0_OUTPUT_SEL = 0x0a for CLK_PFD_REF and* Set GPIO4_OUTPUT_SEL = 0x0b for CLK_PFD_FB
4) A valid output configuration
I never did get an explicit response from you to confirm the HCSL was valid for your board, I expect so but am assuming. You should be able to get outputs (even if PLL is not locked) if the device is configured appropriately.
Ok, hope this helps, in failing that - the prototypes work for you as expected. The good news is I'm able to get this working fine on EVM.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.