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Part Number: CDCE913
When we have measured pulling range of CDCE913, the pulling range was +/-45ppm as a result.We think it is because the crystal connected the CDCE913 does not satisfy requirements written in "Application Guideline" (SCAA085A).But some implementors of crystal told us that C1>20fF is very big value and it makes the size of crystal oscillator very big.We think we should use bigger size of crystal oscillator than now (Abracon: ABM8-27.000MHZ-B2-T, 3.2x2.5mm), but we want it is as small as possible.
What is an important requirement when we search for a crystal oscillator which makes the pulling range wider ?For example, if you told us "C0/C1 must be less or equal than 220, but C1 does not have to be 20fF", it will be very helpfull for us.
By the way, I have send same question to "Email TI" (www.ti.com/.../webform.tsp) not once or twice, but all of them have rejected.What was bad ?
Are you measuring pulling on the EVM or your own PCB? Have you done all to reduce stray capacitance?
Have you set register 0x05[7:3] = 0x1f (maximum value of 20 pF), or otherwise minimized external capacitance allowing the varactor to have the the largest value so it may pull frequency while still meeting the requirement of Cload at the target frequency? Having a large varactor diode will help your pull-range. So if you pick a crystal that allows this maximum value of 20 pF with minimum external capacitance, this could help you achieve your goal.You might also take a look at application note SNAA065A, which talks about designing a vcxo for LMK040xx devices. From this appnote is the recommendation (from section 5.2, Crystal Oscillator Design):"A reasonable range of values for C0 is single digit picofarads, while C1 will have values that may range from less than 10 femtofarads to greater than 20 femtofarads. Compare these values to nominal values listed on data sheets for some candidate crystals. Also remember to calculate the ratio of C0/C1. In practice, this ratio should be between 200 and 300 for pullable crystals."
user5859459By the way, I have send same question to "Email TI" (www.ti.com/.../webform.tsp) not once or twice, but all of them have rejected.What was bad ?
When you say rejected, you received a response? Or a bounced email? I tried submitting a test question and seems to have been accepted. However E2E is the primary support method, so you will want to post your questions to E2E.73,Timothy
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In reply to Timothy T:
> Are you measuring pulling on the EVM or your own PCB?
We have measured it on our own PCB.
> Have you done all to reduce stray capacitance?
We placed CDCE913 and the crystal as close as possible.(The length of wirings is about 5mm).But we did not care other things about stray capacitance.
> Have you set register 0x05[7:3] = 0x1f (maximum value of 20 pF),
We measured pulling while setting register 0x05[7:3].The results is bellow. 0x01 : +/-20ppm 0x04 : +/-44ppm 0x07 : +/-47ppm 0x0a : +/-46ppm 0x0d : +/-45ppm 0x10 : +/-42ppm 0x14 : +/-36ppm
> or otherwise minimized external capacitance allowing the varactor to have the the largest value
We did not place any external capacitance, but we do not know how much stray capacitance is there.
> so it may pull frequency while still meeting the requirement of Cload at the target frequency?
The CL of the crystal on our now PCB is 18pF(typical).(C0: 7pF(maximum), C1: now inquiring)
> Having a large varactor diode will help your pull-range.> So if you pick a crystal that allows this maximum value of 20 pF with minimum external capacitance, this could help you achieve your goal.
As I have shown above, the pulling range was not maximized when setting 0x05[7:3]=20pF.Does it mean that there are some external (stray) capacitance ?
> You might also take a look at application note SNAA065A, which talks about designing a vcxo for LMK040xx devices.> From this appnote is the recommendation (from section 5.2, Crystal Oscillator Design):> "A reasonable range of values for C0 is single digit picofarads, while C1 will have values that may range from less than 10 femtofarads to greater than 20 femtofarads.> Compare these values to nominal values listed on data sheets for some candidate crystals.> Also remember to calculate the ratio of C0/C1.> In practice, this ratio should be between 200 and 300 for pullable crystals."
Do you mean that it is applicable for a crystal connected to CDCE913 ?If so, the required conditions about the crystal is bellow, right? - "1pF <= C0 <= 9pF" (is better) - "C1 < 10fF" or "20fF < C1" (is better) - "200 <= C0/C1 <= 300" (shoude be)
> When you say rejected, you received a response? Or a bounced email?I have received a message on my web browser.I do not remember correctly, but I remember that the message mean "please go back on your browser."
> I tried submitting a test question and seems to have been accepted.> However E2E is the primary support method, so you will want to post your questions to E2E.
OK, I see.
Thank you for your kindly help!I have asked some additional questions in this post.Could you please tell me about them?
In reply to user5859459:
user5859459We placed CDCE913 and the crystal as close as possible.(The length of wirings is about 5mm).But we did not care other things about stray capacitance.
Best practice is to make a ground cutout in the PCB where the crystal is and the traces to minimize stray capacitance. You can estimate your stray capacitance by determining the capacitance when exactly on frequency vs. what the varactor is adding (or set to 0 and add load capacitance manually). Note CDCE913 adds ~1.5 pF capacitance intrinsically.
user5859459We measured pulling while setting register 0x05[7:3].The results is bellow. 0x01 : +/-20ppm 0x04 : +/-44ppm 0x07 : +/-47ppm 0x0a : +/-46ppm 0x0d : +/-45ppm 0x10 : +/-42ppm 0x14 : +/-36ppm
user5859459The CL of the crystal on our now PCB is 18pF(typical).(C0: 7pF(maximum), C1: now inquiring)
It may be that the stray capacitance is resulting in total capacitance with the higher values to be so high that the pulling is reduced. Although I'm surprised... you measured -X ppm and +X ppm. I would have expected more lopsided measurements, such as -X ppm and +Y ppm with respect to your target frequency. Perhaps you're measurements were not with respect to target frequency. The crystal should be 0 ppm in error to target frequency at 18 pF load. Varactor capacitance for Vtune from 0 to 1.8 V is 0.3*XCSEL to 1.3*XCSEL; where XCSEL can be from 0 to 20 pF. As you continued to increase the total capacitance, I would have expected lower and lower frequencies.
Note from figure 6 of SCAA085A as capacitance gets higher, the change in ppm becomes smaller. This is probably what you are seeing... and since the varactor goes from 0.3 XCSEL, the minimum capacitance continues to increase. I was thinking XCSEL was just changing the top end.
To your original question of key parameters to look for for best pulling range, lower CL crystal (so 18 pF load crystal is not a best choice) and minimum stray capacitance will lead to the best pull range. Have you seen the pull range simulator in CDCE913 profile of TI Clock Pro? TI Clock Pro is the EVM tool for CDCE913. This may help you determine what you need for best pull range. I think you next step should be to try a crystal with lower CL.
Thank you for your detailed information !I have not used "TI Clock Pro" ever.I will try it.
I am very sorry for my inaccuracy.I have measured the pulling range as bellow. (1) Prepare base clock source (A) and CDCE913's VCXO clock source (B). (2) Make a cyclic pulse from (A). (3) Make a cyclic pulse from (B). The number of clocks of the cycle is same as (2). (4) Observe (2) and (3) by an oscilloscope. The trigger signal is the positive edge of (2). (5) Measure the phase moving between (3) and (2) in a certain seconds while Vctrl is GND. (6) Measure it while Vctrl is VDD. (7) Calculate the delta of maximum/minimum frequency by using the number of clocks of the cycle, its time to observe and the results of (5) and (6).
"XX" in "+/-XXppm" which I wrote meant the half value of (7).I could not think out other method to observe pulling range in a ppm unit by using our equipments.
Surely, it is shown in figure 6 of SCAA085A that the higher value of CL makes the pulling range narrower.As you say, it seems better to change a crystal with lower CL value.Now, I think that the requirements for a crystal is below. (1) CL : as small as possible (5 ~ 10pF ?) (should be) (2) C0/C1 ratio : between 200 and 300 (should be) (3) C1 : less than 10fF or grater than 20fF (is better) (4) C0 : between 1pF and 9pF (is better)
Could you please confirm whether my understanding is right or not ?If it is right, I will search for such a crystal.
I am sorry for my frequent posts, but a new question came up to us.Please forgive me.
Why the requirement for C1 is "C1<10fF" or "20fF<C1" ?We feel a little strangeness about it.We think that a requirement for a value is usually indicated by only maximum, only minimum or both.Could you please tell me more detail simply ?
Target load capacitance
Parasitic board capacitance
Tuning load capacitance inside the device
I think the pulling range value above the graph is computed incorrectly. Instead of relying on this number, you can just visually look at the curve to see the upper and lower ppm values of the plot to determine the total pull range over the Vctrl range.
In reply to Alan O:
I understanded as below. [Spec of a crystal] C0 : Shunt Capacitance C1 : Motional Capacitance L1 : Motional Inductance Crystal : Load Capacitance [Spec of a PCB] CparBoard : Parasitic Board Capacitance [Setting of CDCE913] CLOAD : Load Capacitance set by XCSEL
-The value drawn in right of "Pulling Range" indicates pulling range directly. But it is less usefull than the value which can be read visually from the curve of the graph.
If there are something wrong, please tell me.
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