• TI Thinks Resolved

LMX2594: SYSREF out can not be synchronized

Part Number: LMX2594

Hi,

     LMX2594 is configured in sysref master mode. SYSREFREQ of LMX2594 is held high .Every time the SYNC input of  LMX2594   changes  from  low then high then low, the LMX2594 is unlocked once.And  there's no definite phase relationship between the sysref out  and the sync signal.

LMX2594 configuration is as below:

0x00=0x641E
0x70=0x0000
0x6F=0x0000
0x6E=0x0000
0x6D=0x0000
0x6C=0x0000
0x6B=0x0000
0x6A=0x0000
0x69=0x0021
0x68=0x0000
0x67=0x0000
0x66=0x3F80
0x65=0x0011
0x64=0x0000
0x63=0x0000
0x62=0x0200
0x61=0x0888
0x60=0x0000
0x5F=0x0000
0x5E=0x0000
0x5D=0x0000
0x5C=0x0000
0x5B=0x0000
0x5A=0x0000
0x59=0x0000
0x58=0x0000
0x57=0x0000
0x56=0x0000
0x55=0xD300
0x54=0x0001
0x53=0x0000
0x52=0x1E00
0x51=0x0000
0x50=0x6666
0x4F=0x0026
0x4E=0x0001
0x4D=0x0000
0x4C=0x000C
0x4B=0x0800
0x4A=0x0000
0x49=0x003F
0x48=0x004E
0x47=0x0049
0x46=0xC350
0x45=0x0000
0x44=0x03E8
0x43=0x0000
0x42=0x01F4
0x41=0x0000
0x40=0x1388
0x3F=0x0000
0x3E=0x0322
0x3D=0x00A8
0x3C=0x0000
0x3B=0x0001
0x3A=0x0001
0x39=0x0020
0x38=0x0000
0x37=0x0000
0x36=0x0000
0x35=0x0000
0x34=0x0820
0x33=0x0080
0x32=0x0000
0x31=0x4180
0x30=0x0300
0x2F=0x0300
0x2E=0x07FE
0x2D=0xC0DF
0x2C=0x1F23
0x2B=0x0000
0x2A=0x0000
0x29=0x0000
0x28=0x0000
0x27=0x0001
0x26=0x0000
0x25=0x8304
0x24=0x0028
0x23=0x0004
0x22=0x0000
0x21=0x1E21
0x20=0x0393
0x1F=0x43EC
0x1E=0x318C
0x1D=0x318C
0x1C=0x0488
0x1B=0x0002
0x1A=0x0DB0
0x19=0x0624
0x18=0x071A
0x17=0x007C
0x16=0x0001
0x15=0x0401
0x14=0xE048
0x13=0x27B7
0x12=0x0064
0x11=0x0064
0x10=0x0080
0x0F=0x064F
0x0E=0x1E70
0x0D=0x4000
0x0C=0x5002
0x0B=0x0018
0x0A=0x10D8
0x09=0x0604
0x08=0x2000
0x07=0x40B2
0x06=0xC802
0x05=0x00C8
0x04=0x0A43
0x03=0x0642
0x02=0x0500
0x01=0x0808
0x00=0x641C
0x00=0x641C

  • Idx,

    SYNC feature gives consistent relationship between RFoutA and Fosc.
    The SYNC pin is re-clocked to the OSCin pin.

    So when you SYNC, I would expect consistent relationship between RFoutA and Fosc.
    Also, the SYSREF can control the delay between RFoutA and RFoutB. However, no where is there any statement about consistent relationship between SYNC and SysREFout.

    Maybe you really want to use the SysRefReq pin that gets reclocked to hte output. As page 32 of the datasheet states:

    As Figure 29 shows, the SYSREF feature uses IncludedDivide and SYSREF_DIV_PRE divider to generate fINTERPOLATOR. This frequency is used for re-clocking of the rising and falling edges at the SysRefReq pin. In master mode, the fINTERPOLATOR is further divided by 2×SYSREF_DIV to generate finite series or continuous
    stream of pulses.

    Regards,
    Dean
  • In reply to Dean Banerjee:

    Hi,
    Thanks for your quick reply.
    There are 3 question.
    Qestion 1. I have also tried repeater mode.But every time the circuit powers up ,the inut sysrefreq and output SYSREF have 2 possible phase relationship.so determistic latency can not be achieved.
    Qestion 2. In master or repeater mode ,when LMX2594 receives SYNC pulse ,it will unlock once .Is this correct?
    Qestion 3. As page 35 of datasheet states:In master mode (SYSREF_REPEAT=0), rising and falling edges at the SysRefReq pin are first re-clocked to the fOSC , then fINTERPOLATOR, and finally to fOUT. This statement implies master mode can be used to generate phase related SYSREF out by using SYSREFREQ?
    Above all,My goal is to get determistic relatioship between input sysref(or sync)and output sysref.Can this goal be achieved, how to achieve it?
    Thanks in advance.
  • In reply to ldx dfdx:

    Idx,

    Q1: We have tested the delay from RFoutA to Fosc and this is consitent. Now with SYSREF on RFoutB, there are dividers after the included divide and you can certainly be off by one phase interpolator clock cycle. So if you are claiming that there is a bimodal distribution of this, have seen this. However, it's not like a 180 degree phase shift, but rather two closer phases.

    Q2: Yes, when you sync, it the VCO will re-calibrate. Actually, I think it only does this if FCAL_EN=1, but not sure.

    Q3: In Master mode, the intention is that the SysRefReq pin is high all the time

    What I think is happening is that you are dealing with the reclocking to the fINTERPOLATOR. I think that if fINTERPOLATOR is a multiple of your input frequency, fOSC, then you can eliminate this uncertainty.

    Regards,
    Dean
  • In reply to Dean Banerjee:

    Hi,
    Thanks a lot for your reply.
    We now still use LMX2594 to generate clock for ADC,its RFoutA really has consitent delay with Fosc input.
    For SYSREF , we have tried pulse mode ,master mode ,and repeater mode,none of them works well to give consitent delay.Now we use LMK0428 to produce SYSREF,and the phase between channels are deterministic。
    I still hope TI can give a method to produce usable SYSREF in deterministic lantency by using LMX2594.
    Thank you!

  • In reply to ldx dfdx:

    Idx,

    The sysref gives consistent delay between RFoutA and RFoutB, but it is reclocked to the Fosc, Finterpolator, and FoutA frequencies.

    This sysref delay does vary with temperature and can be off due to re-clocking, but should be able to produce a known latency between RFoutA and RFoutB. In other words, if you wanted RFoutB rising edge to happen some consistent time after an RFoutA rising edge, this should be possible.

    During characterization, we got the part to SYNC and then we saw that we can adjust the phase relationship.

    So is what you are claiming that if with the same setup condition, the delay between RFoutA and RFoutB is not the same?
    If so, I can check this in the lab later this week, but I'm out of office today.

    Regards,
    Dean
  • In reply to Dean Banerjee:

    Hi,
    The delay between RFoutB and RFoutA may be determined.But please help me check determistic delay between RFoutB(SYSREF) and SYSREFREQ(or SYNC input).Now I find many cycles 0f rfouta variation between RFoutB(SYSREF) and SYSREFREQ(or SYNC input).
    Thanks in advance!
  • In reply to ldx dfdx:

    Idx,

    So Fosc to RFoutA is determinstic
    RFoutA to RFoutB is determiinstic

    But the claim is that SYNC to SysRefReq are NOT deterministic and neither is SysRefReq to RFoutB.
    But as both SYNC and SysRefReq are reclocked by Fosc,, and SysRefREq is further reclocked by the phase interpolator clock and the RFoutA clock, is this a surprise?

    Any divider out of the loop introduces a non-deterministic delay. For the SysRef, ther are additional dividers out of the loop.
    I would love to test this on the bench, but am totally swamped this week.

    REgards,
    Dean