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LMK04610: LMK04610

Prodigy 230 points

Replies: 3

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Part Number: LMK04610

Hi,

This is similar to the issue raised earlier. The loop bandwidth for PLL2 is showing to be > 10MHz for a PFD of 10MHz. But this is not observed at higher PFD frequencies.

We need to generate 105MHz and 10.5MHz from LMK04616. for which the the selected VCO frequency is 5880MHz. This synthesis is not possible with higher PFD frequencies. Kindly clarify if the observed loop bandwidth is a tool issue or configuration issue.

The TICSPro file is attached for reference.

Regards,

Ayesha105MHz_10M_PFD.7z

  • Hi Ayesha,

    I have assigned a responsible engineer to your post. He will get back to you soon.

    Kind regards,
    Lane

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    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

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  • Hello,

    I'll be reviewing the code this week to see what I can confirm about this.

    73,
    Timothy

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect​​​​
    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Timothy T:

    Actually, looking at the open loop and closed loop gain functions, the plotting appears correct for the ~300 kHz loop bandwidth. So I think the returned value is in error. I'll see what I can do to correct this for an updated TICS Pro release.

    73,
    Timothy

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect​​​​
    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

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