Part Number: LMK03328
I am having a problem that the PLL Loss of Lock.
It is known that the output of the N divider is stopped.
(Depending on the output of the STATUS0 pin set by R27 [7: 4]=0x4)
The outputs of the R divider and M divider are working normally.
(Similarly, depending on the setting of R27(R28))
How should we debug from here?
WEBENCH data will be attached
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In reply to Shawn Han:
I'm sorry. I only use CodeLoader.
Is it okay to set up CodeLoder?
I will attach a file.
In reply to user1223309:
Thank you for answering,
>From your Codeload .mac file , you are using PLL1, so PLL2 can be power down by set PLL2_PDN bit.
I tried to disable PLL 2 but the output of the N divider has been stopped continuously.
>Make sure schematic design is no problem, refer to LMK03328 EVM user guide.
The circuit diagram is a power supply configuration similar to EVM. I could not find a problem.
The schematic is as follows.
>Continue to use R27 to read status for "PREREF LOS" . Make sure the reference is detected by LMK03328.
Since PRIREF Loss of Signal did not become active, it seems that the reference clock has no problem.
>R3_mode could choose INT-PLL.
Excuse me, what does R3_mode refer to?I will try integer PLL mode.
To set 0x01 is correct in your clock generation case (LBW= 247kHz), because VCO in a closed loop need time to become stable, otherwise device runs in a wrong VCO frequency.
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