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LMK04000: lmk04000bise

Prodigy 50 points

Replies: 8

Views: 239

Part Number: LMK04000

Hi every one 

In my design i am using LMK04000BISE PLL clock conditioner for my ADC input.  The problem i am facing right now is that

the clock output (CLKOUT1 AND CLKOUT2) which is configured as output for 125MHz from reference input VCXO of 100Mhz. Instead of 125Mhz at the output i am getting offseted output of 120.05MHz which is not

even stable. But to confirm that issue i have tested with the same code configuration with another board(same design configuration) there it was working fine. 

Output Clock Response:

EXPECTED  (MHz) MEASURED  (MHz)
125  120.05
102.4  100.04

  • Hello Vengatesh,

    As I understand, you have eliminated software as a problem by testing two boards with the same configuration.

    I am confused about your expected/measured clock frequencies. It is impossible to get 125 MHz and 102.4 MHz at the same time.
    * Are these different programming configurations? I have a feeling yes.
    * I notice that they have different ppm error...
    > For the 120.05 MHz that is -39600 ppm.
    > For the 100.04 MHz that is -23047 ppm.

    I have a few debugging items for you:
    * What does the lock detect report on LD pin for PLL1 (PLL_MUX = 0x0e) and PLL2 (PLL_MUX = 0x03)?
    * Can you measure the voltage of CPout1 and CPout2 pin on the non-working board? These should not be railed high or low.

    Another debug item to find where some signal may not be as expected, please measure LD pin output frequency when PLL_MUX = the following values.
    * 0x16, PLL1_R. Should be VCXO Frequency / PLL1_R / 2.
    * 0x14, PLL1_N. Should be VCXO Frequency / PLL1_N / 2.
    * 0x0B, PLL2_R. Should be VCO Frequency / PLL2_R / 2.
    * 0x09, PLL2_N. Should be VCO Frequency / PLL2_N / 2.

    * Can you also check the voltage of the LDObyp1 pin (pin 9) and LDObyp2 pin (pin 10).

    73,
    Timothy

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect​​​​
    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Timothy T:

    Hii timothy

    Thanks for your valuble suggestion 

    just now only i saw your reply 

    I will start debugging right now based on your comment and i will reach you soon with the results.

    Thank You very much

  • In reply to Timothy T:

    Hii timothy 

    Based on your debugging  suggestion 

    I have tried two of your suggested methods

    The first one : The LD pin reported as 0 for  (PLL_MUX = 0x0e) andPLL2 (PLL_MUX = 0x03)

    The second thing is voltage output of CPOUT 1 and CPOUT 2 of non working board:

    CPOUT 1 = 0.027V

    CPOUT 2 = 1.292V

    For your reference the schematic is attached with the reply

    Also the LDObypass 1 voltage comes out to be = 2.55V and  LDObypass 2 voltage comes out to be = 1.608V


    Thank You

     

     

  • In reply to Vengatesh Devarajan:

    Vengatesh,

    Timothy is out for the rest of the week, so I'll take a shot at this.

    Based on your charge pump voltages, it seems that PLL1 is not locked. This means that perhaps your 100 MHz VCO frequency is likely a little bit lower than you expect it to be.

    When you program PLL2, (I think PLL2_N), the VCO will calibrate, but if the input reference is low, then so will be the result.

    This device likely has a 2.5 V internal core, so 2.5V LDO output sounds right. Also, some of the VCOs have a special output where the other LDO output is something lower like 1.6 V. So these LDO readings seem very plausable to me.

    So in summary, I think that perhaps PLL1 VCXO frequency might be less than 100 MHz because tuning votlage is close to 0V rail and this is throwing off PLL2.

    REgards,
    Dean
  • In reply to Dean Banerjee:

    Hii Banerjee

    Your  suggestion has guided me lot  and I like to know that whether the internal charge pump of PLL1 has  got damaged.

    To verify this I programmed the PLL1_CP_GAIN register to 111b which corresponds to charge pump current of 400 micro Amps (Earlier it  was configured for 100 micro Amps ) and the output  voltage at CPOUT1 remains same (0.027V). So I suspect that the internal charge pump has got damaged. Again to ensure this I verified same thing with another board (working fine) there the CPOUT1 voltage comes out to be 1.42V.

    And i will be more happy if you provide feedback on this and any other suggestion since I have been debugging on this for past 1 week.

     I and finally i like to know whether the PLL IC has to be replaced ( IF REQUIRED ).

    Thank You

  • In reply to Vengatesh Devarajan:

    Vengatesh,

    To check the charge pump, I would try to slam it to the rails.

    There are two ways to do this:
    Method 1: Program the PLL1_N divider to make direct the VCO to go to 1 MHz and 5 GHz. This should slam it to the rails.
    Method 2: Toggle the PLL1_CP_POL bit. This should make it jump.

    Aside from a chip issue, this could also be the charge pump shorted to ground or not connected the loop filter.

    Regards,
    Dean
  • In reply to Timothy T:

    Dear Banerjee

    Finally I have replaced the PLL chip but the after replacing the chip also the output is still the same situation output is still at 120.05 MHz and no improvement.

    TIMOTHY REPLY

    Another debug item to find where some signal may not be as expected, please measure LD pin output frequency when PLL_MUX = the following values.
    * 0x16, PLL1_R. Should be VCXO Frequency / PLL1_R / 2.
    * 0x14, PLL1_N. Should be VCXO Frequency / PLL1_N / 2.
    * 0x0B, PLL2_R. Should be VCO Frequency / PLL2_R / 2.
    * 0x09, PLL2_N. Should be VCO Frequency / PLL2_N / 2.

    And I have doubt with what the Timothy earlier replied : HOW TO DETECT THE FREQUENCY AT THE LD PIN OUTPUT 

     

    Thank You

     

  • In reply to Vengatesh Devarajan:

    Hello Vengatesh,

    Dean Banerjee
    Method 1: Program the PLL1_N divider to make direct the VCO to go to 1 MHz and 5 GHz. This should slam it to the rails.
    Method 2: Toggle the PLL1_CP_POL bit. This should make it jump.

    Based on Dean's comments, did you find the PLL1 CP voltage go high by either method below?

    Timothy T
    I am confused about your expected/measured clock frequencies. It is impossible to get 125 MHz and 102.4 MHz at the same time.
    * Are these different programming configurations? I have a feeling yes.
    * I notice that they have different ppm error...
    > For the 120.05 MHz that is -39600 ppm.
    > For the 100.04 MHz that is -23047 ppm.

    Can you advise me more about the frequencies you are inputting and outputting [expecting/measuring] during your measurement [at the same time].  I'm still a bit confused by the table you gave.  Can you confirm which output you are inputting/outputting/measuring the frequency at?

    Vengatesh Devarajan
    And I have doubt with what the Timothy earlier replied : HOW TO DETECT THE FREQUENCY AT THE LD PIN OUTPUT 

    Did you try programming these values and got no output from LD pin?  Was the behavior the same on the working board?

    Vengatesh Devarajan

    The first one : The LD pin reported as 0 for  (PLL_MUX = 0x0e) andPLL2 (PLL_MUX = 0x03)
    The second thing is voltage output of CPOUT 1 and CPOUT 2 of non working board:

    CPOUT 1 = 0.027V
    CPOUT 2 = 1.292V

    It is puzzling to me that CPout2 is not railed, but PLL2 LD is low also.

    --------

    As Dean mentioned, the voltages for LDObyp1 and LDObyp2 sounds correct.  One more item to check for DC levels.  Can you advise the DC voltage at CLKinX and OSCin on the IC side of the capacitors?  As I remember, they should be around 1.5 ~ 1.8 V.  From your schematic, I can't tell your circuit for input connections, be aware they should be AC coupled for OSCin and CLKin.  Except that CLKin can accept a 3.3 V CMOS signal when the CLKinX_BUFTYPE mode control bit is set for MOS.

    73,
    Timothy

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect​​​​
    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

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