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LMX2572: LMX2572

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Replies: 7

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Part Number: LMX2572

I having problem with running the chip.   PLL  sets  LOCK but  frequency is not locked.

Using VCO force i was able to run chip only for VCO4 and VCO6  subranges.

What can be a reason for such behavior?

  • Vladimir,

    There are many possibilities:
    1. Invalid refernce presented to LMX2572.
    2. SPI programming not reliable -- try some simple SPI command like POWERDOWN to ensure that device recognizes SPI writes corrrectly.
    3. Power supply current limited
    4. Check programming. Are you using TICSPro? The GUI gives useful feedback for this.
    5. Load default mode in TICSPRO, reset chip (RESET=1, then RESET=0), load all registers.


    Regards,
    Dean
  • In reply to Dean Banerjee:

    Hi  Dean,

    1. Reference clock is OK.

    2,4,5  SPI  is OK,  I write frequency setup every second, no missed setups  for 2-3 hours.

    At first i have used my register setup,  then register setup generated by TICSPRO. I can readback

    all registers and they behave as expected - write and read values are the same(except  readonly registers).

    I have tried  self clearing RESET and  explicit write with RESET=0, no avail.

    3.  It seems, this is the power problem or hardware wiring.

         The chip is powered from two ADP150AUJZ-3.3, one branch connected to VCCBUF, second powers all other pins.

         Visually (by oscilloscope)  there are no problems in power supply.

    Questions:

    1. There is bunch of "bypass" pins, what are expected levels on those pins?

    2. "LOCK"  is locked mostly, no matter that frequency is wrong or unstable,

    sometimes, though, it is not locked..?

  • In reply to vladimir romanchuk:

    6175.LMX2594 Initialization Power Up and Calibration.pdfVladimir,

    OK, it sounds like some of the basic things are running.   It's tricky to think of what would make only two cores work, unless you are misprogramming the device.  When you force the ranges did you try?

    1.  VCO_DACISET_FORCE=1, VCO_DACISET=200

    2. VCO_CAPCTRL_FORCE=1, VCO_CAPCTRL=100

    3.  VCO_SEL_FORCE=1, VCO_SEL = 1,2,3,4,5,6

    For "Lock", if this is based on the "VCO calibration Status" lock detect, maybe this is the issue as you can lose lock with this style and it will not indicate it.

    I don't have a bias level document with the LMX2572, but I have one for the LMX2594, which should be very similar and I am attaching.

    REgards,

    Dean

  • In reply to Dean Banerjee:

     

    Dean Banerjee

    1.  VCO_DACISET_FORCE=1, VCO_DACISET=200

    2. VCO_CAPCTRL_FORCE=1, VCO_CAPCTRL=100

    3.  VCO_SEL_FORCE=1, VCO_SEL = 1,2,3,4,5,6

    Can you clarify - run this settings  with  default N,NUM,DENOM, Fpfd path registers or  with some settings?

    For "Lock"  I use LED connected to MUXOUT (output functionality "Lock detect"), can you clarify about  "VCO calibration Status"?

    I have checked voltages given in "LMX2594 Initialization.."  file. The voltages  are very close, it seems, they are ok.

    Questions:

    1 .  FCAL_EN=0 was mentioned in the given file. But LMX2572 datasheet states: 

    "Enables and activates VCO frequency calibration. Writing register R0 with this bit set
    to a 1 enables and triggers the VCO frequency calibration. Writing 0 to this field is
    prohibited."

    2. In initialization procedure  -

    "4. Program all registers in REVERSE order from highest to lowest

     5. Wait 10 ms

     6. Program register R0 one additional time with FCAL_EN to ensure VCO calibration runs from a steady state".

     So  two  R0 writes are implied separated by 10 ms.  Is this right?

  • In reply to Dean Banerjee:

    Update:  I was able  to run PLL  with TICS Pro register datasets  for all VCOs.

    It seems, PFD_DLY_SEL has big impact on functionality.

    I can not  grasp idea of selecting this parameter from Table 3.(LMX2572 datasheet )

    I will use N in range  256...512 (3200...6400 Mhz / 12.5 Mhz).

    Can you, please, provide more detailed selection guide.

  • In reply to vladimir romanchuk:

    Hi Valdimir,

    You don't have min. N requirement problem because your N's are over 200.
    However, PFD_DLY_SEL still need to be set properly according to the fractional order you have selected.
    For example, if you have selected to use 3rd order, then PFD_DLY_SEL must be either 2 or 3, depending on the VCO frequency.
  • In reply to Noel Fung:

    Hi Dean,
    Now is all working.
    Thank you very much.

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