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  • TI Thinks Resolved

CDCUN1208LP: CDCUN1208 - SPI communication timing

Genius 11390 points

Replies: 4

Views: 129

Part Number: CDCUN1208LP

Hello Team,

we are facing some challenges during the SPI communication with the device.

Things are looking now working, but out of the datasheet there are gray area:

in our first attempt we implemented the SPI write as it is shown in figure 32 on page 30 of the data sheet. There were the following differences:

  • SCL starts at low value to have the same conditions before and after transfer, so the first transition of SCLK was a rising edge 425ns after the falling edge of SCSn
  • write data was supplied via SDI instead of SDO

This seemed to work, but later on we found out that it was not reliable. According to section 8.5.1.1 the chip operates on the rising edge of SCL, but the timing t6 in table 9 suggests that the chip operates on both edges (by the way: I would expect a max delay specification for t6 instead of a min delay). As it is not allowed to toggle SCL while SCS is high, my conclusion was that the falling edge of SCL has to be applied before SCS is released and that timing t8 also applies for the falling edge of SCL.

So the new implementation switches the SCL to low first and de-asserts SCS later. With this new implementation there are no issues so far.

Can you please review and let us know if you have suggestions for further improvements?

Thanks,

SunSet

  • Sunset,

    I don't konw the answer to this question, but assigned it to maybe soneone who has a better chance.

    Regards,
    Dean
  • Hi Sunset,
    It is correct for your operation "the new implementation switches the SCL to low first and de-asserts SCS later. With this new implementation there are no issues so far.".

    Noticed CDCUN1208LP datasheet ever been updated.
    Changes from Revision B (July 2013) to Revision C
    //Added text "At no time should the clock be toggled while SCS is high. CDCUN1208LP should always be used in
    single-slave SPI configuration." in 8.5.1.1.2 Writing to the CDCUN1208LP and 8.5.1.1.3 Reading from the CDCUN1208LP //

    But it seems Figure 32-34 didn't highlight the notes. Thanks a lot for your highlighting in E2E.

    Best Regards,
    Shawn

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  • In reply to Shawn Han:

    Hello Shawn,

    thanks for your inputs.

    can you please clarify the following points:

    I have taken a closer look to the table 9 :

    •  What sounds to me strange is t3, which is called SDO to SCL hold time, while I would have considered SDI to SCL hold time.  
    • t6 is specified as minimum.  From my perspective having a minimum is not optimal. Having a minimum would help to implement a filter  that removes any signal coming before that time but having a max should help in validating the setup and hold time on the receiver side. This is probably what may be more important, having both, even better.
    • Why for t6 we have specified the min time only?

    thanks,

    SunSet

  • In reply to Sunset:

    Hi SunSet,

    A1. You are correct. This is a typo error, we will update it in the next datasheet revision
    A2. I looked through the characterization data but unfortunately this information is not available
    A3. We only have min time for t6 as the SPI timing parameters are not tested on ATE, but rather guaranteed by design

    Kind regards,
    Lane

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

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