This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Part Number: LMK04828
May I know the minimum LOS detection frequency of CLKin0?
Customer want to detect LOS of CLKin0 port under this condition.
CLKin0 : 80kHz, MOS
CLKin_SEL0 : Oputput(push-pull), CLKin0 LOS
Even though customer check that CLKin0 is good and LD1, LD2 are lock, LOS reported as high. It seems like CLKin0 frequency is too low to detect proper LOS detect.
It is around 370 kHz as datasheet claimed. So the 80 kHz LOS detect is not reliable. Customer need an external method (for example, FPGA counter) to know the 80 kHz status.
To design your own Clock Tree solution, visit WEBENCH Clock Architect !
More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.