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LMK04826BEVM: Getting clock outputs without feeding input clocks.

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Replies: 6

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Part Number: LMK04826BEVM

We have purchased evaluation (LMK04826BEVM) Board for internal testing purpose .

We have following quires

1) We are getting outputs without feeding clock input ( Isolated on board Oscillator )

2) we are getting outputs even after disabling the PLL1 and PLL2 through the TICSPro software.

 

  • Hello Bharathkumar,

    The LMK04826 has an internal VCO, which has separate powerdown controls (VCO_PD, VCO_LDO_PD) from the PLL powerdowns. If the VCO is not powered down, and the VCO_MUX is assigned to one of the VCO signals, the VCO and therefore the outputs will still oscillate open-loop. Please confirm that the VCOs are powered down by setting VCO_PD = 1 and VCO_LDO_PD = 1, and check the outputs again.

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    Thank you for your response

    1) We are getting noise on the output  even after selecting power down ( VCO_PD, VCO_LDO_PD ) option. 

    2) VCO/Clock Dist. frequency is showing 0 MHZ in the tool after selecting following Points. Please find software Screen shot

                      CLKin1=0 MHZ

                      OSCin=0 MHZ

                      OSCin Source= External VCXO

            The issue is getting clock outputs and even VCO/Clock Dist. frequency is showing 0 MHZ in software.

             

          

    3) We are using three LMK04826 for JESD204B. We want three LMK's to be in sync. Suggest us which input(CLKin0,CLKin1,CLKin2,Oscin) will enable all the outputs. If possible please provide us the clocking scheme how multiple devices to be connected for JESD204B.

    4) Are these outputs depended on input clock or will it generate from internal VCXO's ??

    Regards,

  • In reply to bharathkumar Nagavelly:

    Bharathkumar,

    1. In your screenshots I observe that the "Device Not Connected" indicator is present, and that the VCO_PD and VCO_LDO_PD bits are set to 0. To help debug this issue better, can you configure TICS Pro to a state where you believe there should be no output frequency, use "File -> Save" to generate a .tcb file containing the settings, and upload this for my inspection?
    2. This software is not a live register map like a JTAG debugging chain. The software has many fields which are calculated and inferred from a combination of user input and software-side register settings. The VCO frequency is inferred from the user-specified CLKin/OSCin settings, the PLL2 R divider, and the PLL2 N divider. As such, the software can say the VCO frequency is 0 Hz, but this does not somehow force the VCO frequency to 0 Hz inside the IC - the VCO frequency range is characterized in the datasheet. In fact, in the screenshot, the VCO frequency box is highlighted red; hovering the mouse over the VCO frequency box will show a tooltip indicating that 0 Hz is not a valid frequency for the VCO.
      Consider changing the output format to "Powerdown" on outputs that are unused or disabled.
    3. The LMK04826 outputs are divided down from the clock distribution frequency, which is the output of the VCO_MUX. The VCO_MUX has three configurations: VCO0, VCO1, and CLKin1 for distribution mode. Distribution mode causes the LMK04826 to behave like a buffer/divider for the CLKin1 input. VCO0 and VCO1 require at a minimum that PLL2 is active and locked to a frequency, which is supplied from OSCin. If LMK04826 is used as a cascaded PLL, the OSCin input is driven by the VCXO in PLL1, which takes as a reference one of the inputs CLKin0, CLKin1, and CLKin2. So there are many configurations which allow for use of all the outputs, depending on the system needs.
      Ensuring that multiple LMK04826 are in sync is a somewhat complex topic. There are multiple methods to establish sync across multiple devices. The powerpoint in this post is a good overview of the available methods. I cannot design a system in an E2E post, but I can review a system configuration and make recommendations.
      Multi-LMK SYNC.pptx
    4. The outputs will always be related to the inputs:
      1. In distribution mode, output = input / CHDIV
      2. Using PLL2, output = input * NDIV2 / (RDIV2 * CHDIV)
      3. Using PLL1 and PLL2, output = input * NDIV1 * NDIV2 / (RDIV1 * RDIV2 * CHDIV)
        Note that CHDIV can be the channel divider or the SYSREF divider, depending on the chosen source for the output.

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    Thank you for response. I will update you 

    Regards

    N Bharath Kumar

  • In reply to bharathkumar Nagavelly:

    Hello,

    We haven't heard from you in some time, so I'm marking this thread as resolved. Let me know if this issue requires further attention.

    Regards,

    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    Hello Darek

    Please find the attached setup file(.tcs).

    We have implemented as per you suggestions even then output remains same. 

    We are getting clock outputs even after disconnecting on board Oscillator.

    Regards

     N Bharath Kumar

    OSCin VCO1.tcs