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LMK03328EVM: PLL is not locking

Intellectual 290 points

Replies: 6

Views: 124

Part Number: LMK03328EVM

I am inputting a LVDS 10.949297MHz clock on PRIREF.  I have various frequency tables loaded into the EEPROM to get 44MHz (4x), 88MHz (8x), and other frequencies (based on PLL1).  I'm using TICS Pro, PRIREF = Diff Input, Max Gain, DIFFTERM_PRI, and AC_MODE_PRI.  The clock at PRIREF looks pretty good and is a 422mVpk-pk, 1.35ns risetime, ,829ps fall-time.  I measured this with a differential probe.  I don't believe the PLL is locking for AC-LVDS outputs (from PLL1) as only the desired frequency is displayed for a short period of time and seems to be fluctuating.  I do have an output as CMOS(+/-) sourced from PLL2 which seems to be fine.  I originally checked out my design with the LMK03328 EVM but CMOS(+/-) signal ended input clock and outputs.  I then copied those settings changing the input & output to LVDS accordingly and loaded that into the PLL on my PWB.  I did look at this thread http://e2e.ti.com/support/clock-and-timing/f/48/t/761411?LMK03328-How-to-debug-PLL-Loss-of-Lock in addition to looking at section 10 in the datasheet and adjusting some of the register settings according.  Changed R29.7, R51.7 to 1.  Changed REFSEL from Low to Hi.  Changed R50.3 & R50.1 from 1 to 0.  Changed R50.2 and R50.0 from 0 to 1.  Changed R50.7 from 1 to 0.  Changed R29.3 from 0 to 1.  The new load into the EEPROM produced the same results where I'm not getting a stable LVDS output clocks.  I don't understand why the LMK03328 is not locking for the LVDS outputs.         

  • Hi Kerry,

    PLL lock status is not relevant to output format. Can you start from the basics and get the PLL locked at a simple frequency first? For example, you can change the input frequency to 50MHz then load default Ticspro configuration, change "INSEL_PLL1" from "Pin Select" to "PRIREF". PLL lock status can be observed on status pins.

    Regards,

    Hao

  • In reply to Hao Z:

    How do you put screen captures?  Do you have an email so I can send you screen captures.  I did look at OUT7 which is 10.4926MHz and is fine.  OUT4 is mostly high with a periodic pulse low.  Original TCS Pro Settings.docx

  • In reply to Kerry Tracey:

    Here's one WEBENCH: LMK03328 88MHz FREF_FPGA.pdf

  • In reply to Kerry Tracey:

    I don't have the default TICS Pro configuration but tried to watch the video but it skips over setting for PLL2.  It turns out on the LMK03328 EVM that outputs 1-6 are locked and output 7 is not.  So this is the opposite problem than my PWB.   Here's my TCS file that partially works on both boards: PLL1 TICS Pro FREF 44MHz.tcs

  • In reply to Kerry Tracey:

    Looks like changing the LF Type to 2nd Order LF for PLL 1 only fixed the problem.  What does this selection do?

  • In reply to Kerry Tracey:

    Hello Kerry,

    Fractional order can help with spur optimization but it doesn't affect PLL lock status. I loaded the "PLL1 TICS Pro FREF 44MHz.tcs" that you attached previously and all outputs look good to me and both PLLs locked with no problem. If you are using TI EVM, then go to Ticspro -> Default Configuration (in the tool bar) -> EVM default just for a quick sanity check.

    If you are not using TI EVM, then there may be a hardware problem because the configuration looks good to me.

    Regards,

    Hao