LMK04100: Audio system clock PLL
Part Number: LMK04100
Our customer wants to get better Jitter suppression performance from LMK04100 or LMK04208.
Their input clock is 44.1KHz with 80nsec jitter, output are is x512=22.579MHz and x1024=45.158MHz.
How can we optimize loop filter of LMK04100 and LMK04208?
PLLatinum Sim are not supported those devices. Which simulation tool can we use?
They want to see simulation result of "Lock time" and "output Jitter".
We will be adding the other LMK parts to PLLatinum sim in the future, however in the meantime, perhaps you can find the Clock Architect tool of use. http://ti.com/clockarchitect
Attached is a document on using it for dual loop simulations.
0550.Using Clock Architect for Dual Loop PLLs - in dual and single loop mode, 2017-03-21.pdf
To design your own Clock Tree solution, visit WEBENCH Clock ArchitectMore information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html
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In reply to Timothy T:
Thank you for your suggestion.
I will let our customer knows this tool and try to optimize dual loop filter parameter.
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