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LMK04133 / Clock Design Tool

Other Parts Discussed in Thread: LMK04133

Hi,

We are considering LMK04133.

・input frequency 25MHz

・output frequency 125MHz/LVCMOS and 1000MHz/LVPECL

・VCXO 30.72MHz

We would like to know the recommended register settings. However, Clock Design tool falls in simulation.

What causes this problem? Please let me know the recommended divider/VCO settings.

Best Regards,

Kato

  • Instead of 30.72 MHz VCXO, I recommend to use VCXO frequency that allows f_vco/f_vcxo to be an integer value, which maximizes the PLL2 phase detector frequency for best performance. Better VCXO frequency options are 25, 40, or 50 MHz.  Let me know which one is preferred, then I can help advise on PLL divider settings.  Also, what are the output frequency/format assignments?

    Regards,
    Alan

  • Hi Alan - san,

    Thank you for the reply.The outputs are 125MHz/LMCMOS and 1000MHz/LVPECL.

    Please let me know the settings for 25MHz VCXO, and 30.72MHz just in case.

    Best Regards,

    Kato

  • Hi Kato-san,

    Here is a suggested LMK04133 configuration that can meet the customer's frequency plan with a 25 MHz VCXO.  I don't recommend using 30.72 MHz VCXO since it would require PLL1 and PLL2 to operate with low PD frequency (due to large PLL N/R divide values) and result in sub-optimal performance.

    Regards,

    Alan