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WEBENCH® Tools/LMK03328: Clock and Timing

ttd
Mastermind 7670 points
Part Number: LMK03328

Tool/software: WEBENCH® Design Tools

Dear Technical Support Team,

I'd like to implement appropriate PLL settings. Especially loop filter with WEBENCH.

Here is my WEBENCH project.

https://webench.ti.com/wb5/OpenPublicSharedProject.jsp?id=153EC8632C794927&s=c

I changed  from auto value to C2=33nF myself on Webench (Basic ⇒Advanced mode on loop filter tab)

In may case, PLL settings are based on fractional value. So I should select 33nF based on Code Loader suggestion below.

■Questions,

I'd like to set minimum jitter implementation.

Could you check my webench and code loader?

If I have mistake, could you point out?

■My target clock

Input Frequency：50MHz

Output Frequencies: 266.625MHz　 LVDS  &  125MHz    LVDS

Output clock Jitter:  inside 10ps peak to peak

■My project (Webench and Code Loader)

Webench

https://webench.ti.com/wb5/OpenPublicSharedProject.jsp?id=153EC8632C794927&s=c

Code Loader

(Could you change from .pdf to .mac? E2E doesn't accept .mac for upload)

4174.LMK03328.pdf

Best Regards,

ttd

  • 0
    TI__Expert 3055 points

    Hi TTD,

    I am attaching a revised mac (as pdf) file + example phase noise plots with this configuration.

    Main changes:

    -Moved 266.625 MHz output to Out4/5

      • When possible, it is best to isolate different frequency outputs to reduce crosstalk
      • Out0:3 prefer outputs from PLL2, Out4:7 prefer outputs from PLL1

    -Enabled doubler->higher PFD which is better

    -Change VCO2 to be 5000 to be in integer mode which has better performance than fractional mode

    -Optimized loop filter settings

    Regards,

    Zoe4174.LMK03328_rev2.pdf

  • 0 in reply to Zoe Nuyens
    Mastermind 7670 points

    Hi Zoe Nuyens,

    Thank you for your reply.

    ①

    Your result of phase noise plots shows low RMS jitter.

    How do you estimate loop filter value (C1/C2/R2/R3)  ? Do you calculate them yourself?

    I have trying  Webench based on your .mac, however  Webench  doesn't show your value of R and C.

    I'm not familiar with PLL and loop filter development , so I'd like to use auto value with Webench.

    For your information, attached my Webench pdf .

    Webench_Zoe_mac.pdf ⇒　Set your .mac (Loop filter value (C1/C2/R2/R3) and PLL (N+Fractional)) 

    Webench_Zoe_mac.pdf

    Webench_Zoe_mac_LF_Change_C2_only.pdf:  Set your .mac (Loop filter value (Change C2 only(3.3nF or 33nF) and PLL (N+Fractional)). C1/R2/R3 are selected by Auto 

    Webench_Zoe_mac_LF_Change_C2_only.pdf

    ②

    Did you select C2=3.3nF for Fractional(5332.5MHz) and C2=33nF for integer(5000MHz) ?

    Best Regards,

    ttd

  • 0 in reply to ttd
    TI__Expert 3055 points

    Hi TTD,

     

    I did use the 3.3 nF for the integer PLL and the 33 nF for the fractional PLL loop filter C2. When determining the loop filter settings, I chose the final values based on the experimental results.

     

    To use Webench, here would be my suggestions:

    1. Consider if any of the VCO frequencies chosen by Webench could be exchanged for a VCO frequency that uses an integer PLL
    2. Change the PFD frequency to simulate enabling the input doubler (i.e. if your input frequency is 50 MHz, set the PFD frequency to be 100 MHz)
    3. For integer PLLs:
    1. Set C2 to whatever value you plan to use
    1. Use the recommended loop filter settings (you may be able to find better ones experimentally, but the recommended settings should be a good start)
    1. For fractional PLLs:
    1. Webench does not include fractional spurs in its loop filter optimization, so it is better to experiment with different loop filter components & other settings for outputs that have a lot of spurs/high magnitude spurs
    1. On the outputs tab, look at the jitter including spurs
    1. Generally, you will want to have a charge pump gain that is less than 6.4 mA (the setting automatically selected by Webench)
    1. Reducing the charge pump gain will reduce the bandwidth which is helpful to reduce the magnitude of fractional spurs & their contribution to RMS jitter
    2. If the output tab shows a large number spurs & high magnitude spurs, you probably want to reduce this by a few settings (my revised configuration used 1.6 mA for example)
    1. Fix C2 to whatever value you plan to use
    2. Change the randomization (dither) to weak
    1. Modify the loop filter components until the jitter including spurs is a reasonable value (Table 8.6 of the datasheet gives an idea for this)
    1. If you enter the loop filter components from my revised configuration, Webench simulates RMS jitter of ~157 fs for the 266.625 MHz output, fairly close to my measured results

    Regards,

    Zoe

  • 0 in reply to Zoe Nuyens
    Mastermind 7670 points

    Hi Zoe,

    Thank you for your reply.
    Your advice is helpful for me to reduce jitter.
    I have additional questions about your answer.

    ①You changed reducing charge pump current for Fractional PLL to reduce spur.
       Is it effective for integer PLL to reduce jitter when reducing charge pump?

    ② You selected 325/ 1000 for Fractional PLL and dither is set "weak"
        It seems that "325/1000" is same setting compered to "13/40".
        Are my understandings below Correct?

    ・"325/1000"(your setting) ⇒ Correct setting for dither "weak"
    ・"13/40"(my setting) ⇒ Not correct setting for dither "weak". should be disable.



    Best Regards,
    ttd

  • 0 in reply to ttd
    TI__Expert 3055 points
    1) Generally, this is not helpful. I would recommend using 6.4 mA as a starting point for integer mode.
    2) Yes, that's correct.