CDCI6214: CDCI6214: Cant get an output signal on Y1 - Y4. Cant get the PLL to lock

Hello Maximilian,

If ch#_sync_delay > 0, then you must have ch#_sync_en = 1 to have the output operate.
Since ch1_sync_delay = 6 in your configuration, you should change it to 0 or set R38[10] = 0x26[10] = ch1_sync_en = 1.
Also, I noticed your output divides were set to 0 for ch(2,3,4)_iod_div. So this would power down the output.

This could address your no output issue. I've not confirmed the PLL lock from EEPROM start at this time.
Also, did you generate your register map using TICS Pro? In the software you can configure the the device, the save a txt file with all the hex register values. Maybe this will help your situation.

Please let me know if you still face the PLL unlock issue.

73,
Timothy

Hello Maximilian,

In review the config you sent I found that...
* ch1_sync_en = 0, but ch1_sync_delay = 1. This will prevent an output. I changed ch1_sync_delay = 0 to ensure an output.
* On the EVM PRIREF is configured for AC differential, so I changed ref_inbuf_ctrl from LVCMOS to AC Differential (but it is LVCMOS in dump below)
* I had to chnage ch1_outbuf_ctrl from HCSL to LVPECL to see an output (but it is HCSL in dump below, provided your output is configured for HCSL, no issue)
* I had to change ch4_outbuf_ctrl from HCSL to LVPECL to see an output (but it is HCSL in dump below, provided your output is configured for HCSL, no issue)
* I had to change ch2_iod_div, ch3_iod_div, and ch4_iod_div from 0 to non-zero to see an output... I've set them for the frequencies listed below in the register dump I provide.
Y0 = 50 MHz from REF
Y1 = 50 MHz from REF
Y2 = 75 MHz
Y3 = 100 MHz
Y4 = 200 MHz

With the small variations to the config, I was able to program the EEPROM and have PLL lock all clock outputs operate.
Confirm an LVCMOS signal to pin 5, REFP.
- I've provided the register dump below you could program that preserves LVCMOS on inputs and HCSL for output formats on Y1 & Y4.

It was my observation that without changing the input to AC differential, I was unable to get the PLL to lock. I used a SigGen at 50 MHz and 5 dBm into a balun into SMA_REFP&N.
> Perhaps there is something with your input causing some grief. Can you measure and show your input waveform?
> Using AC differential, even when I removed the balun and provided 5 dBm into SMA_REFP single ended, the device still seemed lock and provide output.

Please try the register dump below and verification of the input. Let me know how it goes.

73,
Timothy

0x00460000
0x00450000
0x00440000
0x00430020
0x00420200
0x00410F34
0x0040000D
0x003F4210
0x003E4218
0x003D1500
0x003C0018
0x003B1063
0x003A0008
0x00398A51
0x00380009
0x00370003
0x00360000
0x00358000
0x00340008
0x00338861
0x00320031
0x00310006
0x00300000
0x002F8000
0x002E0008
0x002D0A51
0x002C0011
0x002B0008
0x002A0000
0x00298000
0x00280008
0x00270851
0x00260009
0x0025C001
0x00240000
0x00238000
0x00220050
0x00210007
0x00200000
0x001F1E72
0x001E5140
0x001D000C
0x001C0000
0x001B0E00
0x001A0E01
0x00190406
0x00180601
0x00170580
0x00160000
0x00150000
0x00140001
0x00130000
0x0012FFFF
0x001126C4
0x0010921F
0x000FA037
0x000E0000
0x000D0000
0x000C0000
0x000B0000
0x000AA4C4
0x0009A4C4
0x00080001
0x00070C0D
0x0006152C
0x00050008
0x00040000
0x00030000
0x00020000
0x00016B44
0x00001000

Hello Maximilian,

Maximilian Rentschler said:

As a input signal I am using a 25Mhz square-wave which is generated with a Arbitrary Generator.

This was from above...

Maximilian Rentschler said:

I sent you a picture of the input signal. Its a 50Mhz signal from a SigGen.

The prior registers I sent assume 25 MHz input.  If you are using 50 MHz input, then this could be an issue.

I would boil the troubleshooting down to 4 items.

1) Ensure you are indeed programming the device.

If it ever got programmed into a mode where I2C was ignored, the way to get out of this is power up with  EEPROMSEL and REFSEL floating and RESETN/SYNC at VDDREF level.  Sounds like you're probably already doing that, but be sure the RESETN is high.

Maximilian Rentschler said:

I am leaving the EEPROMSEL and REFSEL pin floating while selecting the REF-Input via ref_mux

2) A valid input & input configuration

Maximilian Rentschler said:

I sent you a picture of the input signal. Its a 50Mhz signal from a SigGen.

As for the signal itself, it does appear to meet the requirements for a CMOS in terms of it's amplitude being from ~0 V to ~3.3 V.  Provided you can see the input on Y0, everything should be good.  You might consider testing with ip_byp_mux = 0 for output of REF direct.  If you have a frequency counter synced to your sig gen, this would be the most accurate way to ensure CDCI6214 is getting your input signal properly.

If any trouble, I would try the AC-differential mode with a smaller swing, ~1.5 Vpp.  Even if you can only provide it to the single input for test purposes.

Once all inputs considerations are covered, just be sure the output terminations are configured correctly.  For example on our EVM, I had to change to a non-HCSL output to see the clock.

3) State of the PLL lock.

You are observing this on the output pin.  You should still be able to get outputs even if it is not locked.  You may need to set cal_mute = 0 to get those outputs.

A useful method to troubleshoot PLL lock failure is to look at debugging outputs of CLK_PFD_REF (from input) & CLK_PFD_FB (from VCO).  These signals when output from two status pins should be phased locked with respect to one another.  If you're not locked, these outputs should give you clues as to why not.. for example if one frequency is slightly higher or lower, or if a clock isn't present at all.

* Set GPIO0_OUTPUT_SEL = 0x0a for CLK_PFD_REF and
* Set GPIO4_OUTPUT_SEL = 0x0b for CLK_PFD_FB

4) A valid output configuration

I never did get an explicit response from you to confirm the HCSL was valid for your board, I expect so but am assuming.  You should be able to get outputs (even if PLL is not locked) if the device is configured appropriately.

--

Ok, hope this helps, in failing that - the prototypes work for you as expected.  The good news is I'm able to get this working fine on EVM.

73,
Timothy