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LMK04610: LMK04610 Design Verification

Ayesha fakruddin
Intellectual 360 points
Part Number: LMK04610

Hi,

We are designing LMK04610 in single PLL2 mode with PLL1 bypass. the input to LMK is a 100MHz differential LVDS input to CLKin0 port. The requirement is to generate 3 otputs of 90MHz and 4 outputs of 9MHz (Sysref signals).  The PFD frequency is 10MHz and the VCO frequency is configured to 5850 MHz. The N divider value shall be 117.

For the above mentioned settings, the PLL2 loop bandwidth calculated by the tool is >10 MHz. Please clarify if this is a tool issue or configuration issue.

Regards,

Ayesha

 

  • 0
    Intellectual 360 points

    Please find the TICSpro files attached for reference90MHz_tics2.7z

  • 0 in reply to Ayesha fakruddin
    TI__Mastermind 28530 points

    Hello Ayesha,

    Thanks for attaching the config file!  Out of curiosity, did E2E prevent you from attaching a .TCS file?  I've seen that feedback before, but I was able to attach a .TCS file... if this is true, I'll provide some feedback to the E2E team to allow .TCS file attachments for any user.

    I presume your reference is clean, and therefore you are using single loop instead of dual loop.

    I was able to improve the setup by using a 50 MHz phase detector frequency.  So I updated PLL2_RDIV = 2.  To achieve a VCO frequency of 5850 MHz with a 50 MHz PDF frequency, I set PLL2_PRESCALER_TOP = DIV3 and PLL2_NDIV = 39.

    Then when I loaded the device config into the PLL2 Loop Filter calculator and designed a 200 kHz loop bandwidth filter, it appeared to have no issue.  I then applied these settings back to the config, please find attached for your reference.

    73,
    Timothy

    90MHz_tics2, TT.tcs

  • 0 in reply to Timothy T
    Intellectual 360 points

    Hi Timothy,

    Yes we are using a clean source and hence bypassing PLL1. Yes, I could not attach a .tcs file and hence converted it. 

    I need to generate 90 MHz and 9 MHz clock. Its the PLL2_PRESCALER_TOP output which would get divided to 90MHz. So setting it to 3 would give me 1950 MHz and this frequency cannot be divided down to 90 MHz. So, I need to set the PRESCALER to 5 to get 1170MHz and the PFD to 10MHz.

    However, the issue with loop bandwidth is observed only at high N divider value (or low PFD frequency). Please let me know the reason for this.

    Regards,

    Ayesha 

  • 0 in reply to Ayesha fakruddin
    TI__Mastermind 28530 points

    Hello Ayesha,

    Sorry for my mistake, please find attached a corrected file.  By using a VCO frequency of 5940 MHz and prescaler of 3, you're able to get the 90 MHz & 9 MHz out using output dividers of 22 and 220.  The PLL2 N divider is 99.  This setup is a bit better because the phase detector is able to be 20 MHz instead of 10 MHz.

    I'll have to look into it more to see if I can find why the calculated loop bandwidth is returning in error.  It almost seems as if there is a 10 in front of the proper value.  It so happens with the 20 MHz PDF in the file above, this error doesn't manifest.

    73,
    Timothy

    90MHz_tics3, TT.tcs