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CDCM6208: LOS status issue

Sho Ogane
Genius 5575 points
Part Number: CDCM6208

Hi all.

My customer set register 4 is 0x30, and REF_SEL=Low.
In this case, when the device is powered on and configure setting, PLL_unlock and REF_LOS signals are repeated occurrence / release.
After customer sets ResetN (Reg3_bit6)  changed to 1 from 0, PLL is locked and LOS is released.

Is the reset necessary in this setting?

Best Regards,
Sho

  • 0
    TI__Mastermind 28530 points
    Hello Sho-san,

    Can you share with me the full power-up sequence they use with programming?

    73,
    Timothy
  • 0 in reply to Timothy T
    TI__Mastermind 28530 points
    My current understanding is that:
    - Device has REF_SEL pin = Low
    - RESETN/PWR pin becomes high.
    - PDN pin is high (or floating)
    - SYNCN pin is high (or floating)
    - SI_MODE1, SI_MODE0 pins = Low, Low for SPI or High, Low for I2C.
    - Device is programmed using I2C or SPI.

    Then the customer programs the full register map.
    - Register 3, bit 6 (RSTN) = 1
    - PLL is unlocked
    - REF_LOS is low (meaning there is an input signal present).
    > This is measured on [on STATUS0 pin if Register 3, bit 8, ST0_LOR_EN = 1 or STATUS1 pin if Register 3, bit 11, ST1_LOR_EN = 1]

    When they change Reg3 bit 6 (RSTN bit) from 0 to 1.
    - PLL is becomes locked.
    - REF_LOS is low (meaning there is an input signal present).

    Note,
    As long as RSTN bit = 0, there should be no outputs/not locked.
    When you say in subject LOS status issue,

    73,
    Timothy
  • 0 in reply to Timothy T
    Genius 5575 points

    Hi Timothy-san

    Thank you for your reply.
    Your understanding is correct.

    I have one more information.
    The following setting, CDCM6208 can normal operation when it is powered on.
    [Reg4=0x20EF、REF_SEL=open]

    The different is REF_SEL status, abnormal operation is REF_SEL=L and normal operating setting is REF_SEL=H(open)
    REG 4 setting is be optimized for REF_SEL=L. I checked the table 5 in datasheet. (Table 5. Input MUX Selection)

    I don't know why we need to RESET using REF_SEL=L. 

    And power sequence is following.
    All power supply timing is same time, ResetN become 1 from 0 200ms later from power supply, and wait 10s, my customer set register.
    2.5V : DVDD, VDD_PRI, VDD_SEC
    1.8V and 3.3V : PLL power and IO power

    Best regards,
    Sho

  • 0 in reply to Sho Ogane
    TI__Mastermind 28530 points
    Hello Sho-san,

    Can you confirm the interface type used? I2C or SPI?

    73,
    Timothy
  • 0 in reply to Timothy T
    Genius 5575 points

    Hello Timothy-san

    Thank you for your support.
    The interface type is SPI.

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    TI__Mastermind 28530 points

    Hello Sho-san,

    I apologize for the slow progress on this and all the questions...

    I reviewed the programming of 0x0030...
    bits[15:14] = 0: Smart MUX Pulse Width selection is disabled.
    bits[13] = 0: AUTO SmartMux
    bits[12] = 0: Ignored because AUTO SmartMux mode.
    bits[11:8] = 0: PLL R /1.
    bits[7:6] = 0: secondary input buffer is CML
    bits[5] = 0: Secondary input disabled  [For auto mode, this must be enabled]
    bits[4:3] = 1: Primary input buffer is LVDS
    bits[2] = 1: Primary input enabled
    bits[1] = 0; 1.8 V supply for Secondary input [should be 1 for best performance for 2.5/3.3 V supply]
    bits[0] = 0; 1.8 V supply for Primary input [should be 1 for best performance for 2.5/3.3 V supply]
    --> This setup is technically invalid because in AUTO smartmux mode but both reference are not enabled.

    I reviewed the programming of 0x20EF

    bits[15:14] = 0: Smart MUX Pulse Width selection is disabled.
    bits[13] = 1: Smart MUX is set for Manual.
    bits[12] = 0: Primary input selected at all times.  (Set to 1 so that SECONDARY input is selected when REF_SEL = H).
    bits[11:8] = 0: PLL R /1.
    bits[7:6] = 3: secondary input buffer is Crystal
    bits[5] = 1: Secondary input enabled
    bits[4:3] = 1: Primary input buffer is LVDS
    bits[2] = 1: Primary input enabled
    bits[1] = 1; 2.5 V/3.3 V supply for Secondary input
    bits[0] = 1; 2.5 V/3.3 V supply for Primary input
    --> This setup seems to always select PRIMARY input.  Primary is configured as LVDS input buffer.

    I cannot be sure of the behavior of the REF_SEL pin for the Reg4 = 0x0030 case because it is not valid.  However for the 0x20EF case, I would expect the REF_SEL pin to have no effect because bit[12], SMUX_REF_SEL = 0.  This must be set to 1 so that the REF_SEL can pick between PRIMARY and SECONDARY reference.

    Is the intention to use an LVDS signal at the primary input only for the CDCM6208 reference?

    Is the intention to be able to switch between PRI & SEC reference using REF_SEL pin?

    What is the reference frequency and signal level at PRI & SEC input?

    This is on custom board or EVM?

    If I have full programming, this may help with troubleshooting.

    73,
    Timothy

  • 0 in reply to Timothy T
    Genius 5575 points

    Hi Timothy-san,

    Thank you for your support.

    Sorry, My information was wrong. Customer setting is 0x03EF, not 0x0030.
    Please check it again, sorry...

    I comment the below.

    Is the intention to use an LVDS signal at the primary input only for the CDCM6208 reference?
    ==> Yes, my customer uses primary input only and input type is LVDS.

    Is the intention to be able to switch between PRI & SEC reference using REF_SEL pin?
    ==>Yes, when my customer set REF_SEL pin = LOW, LOS signal is repeated occurrence / release.

    What is the reference frequency and signal level at PRI & SEC input?
    ==>Input frequency is 155.52MHz and  2.5V/3.3V LVDS.

    This is on custom board or EVM?
    ==>Customer board.

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    Genius 5575 points

    Hi Timothy-san

    How about my question?
    Please check the 0x03EF register.

    Customer and I would like to know whether they must reset device or not when they set 0x30EF.

    ///////////////////////////////////////////
    My customer set register 4 is 0x30EF, and REF_SEL=Low.
    In this case, when the device is powered on and configure setting, PLL_unlock and REF_LOS signals are repeated occurrence / release.
    After customer sets ResetN (Reg3_bit 6)  changed to 1 from 0, PLL is locked and LOS is released.

    The following setting, CDCM6208 can normal operation when it is powered on.
    [Reg4=0x20EF、REF_SEL=open(internal pull up=High)]

    The different is REF_SEL status, abnormal operation is REF_SEL=L and normal operating setting is REF_SEL=H(open)
    REG 4 setting is be optimized for REF_SEL=L. I checked the table 5 in datasheet. (Table 5. Input MUX Selection)

    I don't know why we need to RESET using REF_SEL=L. 
    ///////////////////////////////////////////

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    Genius 5575 points

    Hi Timothy-san

    Do you have any update?
    Please give me your reply.

    Best Regards,
    Sho 

  • 0 in reply to Sho Ogane
    Genius 5575 points

    Hi Timothy-san

    I would like to get information whether we should do reset the device at 0x03EF setting to release the LOS and unlock status.
    My customer would like to know it only. If we need to operate reset, we want to know the reason.

    I think I don't need to do reset device, however at setting this register setting(0x03EF), my customer need to do reset after power on device to release the LOS and unlock status.

    I must answer of this issue to my customer until the Friday in this week.

    Best Regards,
    Sho 

  • 0 in reply to Sho Ogane
    TI__Mastermind 28530 points

    Hello Sho-san,

    I apologize, I was out of the office last week.

    Sho Ogane said:
    Is the intention to use an LVDS signal at the primary input only for the CDCM6208 reference?

    ==> Yes, my customer uses primary input only and input type is LVDS.[/quote]

    Sho Ogane said:
    Is the intention to be able to switch between PRI & SEC reference using REF_SEL pin?


    ==>Yes, when my customer set REF_SEL pin = LOW, LOS signal is repeated occurrence / release.[/quote]

    Ok, so with REF_SEL pin = LOW, PRI_REF should be selected. When you say LOS signal is repeated occurrence / release. Do you mean that LOS signal turns on and off, on and off for a period of time, then it stays off (released)?


    Sho Ogane said:
    What is the reference frequency and signal level at PRI & SEC input?

    ==>Input frequency is 155.52MHz and 2.5V/3.3V LVDS.[/quote]

    Please be sure about table 21, register 4:

    If connection at SEC_REF. disable SEC_REF input.
    If LVDS at SEC_REF. Set LVDS mode (currently Crystal mode).
    --

    However I think your point is you are using 155.52 MHz LVDS to PRI_REF and no input to SEC_REF. In this case SEC_REF input should be disabled, so I would recommend a setting like 0x30CF to disable the secondary input.

    Sho Ogane said:
    My customer set register 4 is 0x30EF, and REF_SEL=Low.
    In this case, when the device is powered on and configure setting, PLL_unlock and REF_LOS signals are repeated occurrence / release.
    After customer sets ResetN (Reg3_bit 6) changed to 1 from 0, PLL is locked and LOS is released.

    Sho Ogane said:
    The following setting, CDCM6208 can normal operation when it is powered on.
    Reg4=0x20EF、REF_SEL=open(internal pull up=High)

    I will check with a co-worker to see if they know more about this case. My understanding is REF_SEL shouldn't matter for this programming. However since SEC_REF is not connected, please disable (like Reg4 = 0x30CF) the input and let me know the result.

    73,
    Timothy

  • 0 in reply to Timothy T
    Genius 5575 points

    Hi Timothy-san

    Thank you for your continuous support.
    I am sorry to ask you so many times.

    Timothy-san
    >Ok, so with REF_SEL pin = LOW, PRI_REF should be selected. When you say LOS signal is repeated occurrence / release. Do you mean that LOS >signal turns on and off, on and off for a period of time, then it stays off (released)?
    ==>It doesn't stay off, LOS signal repeat on and off.

    >My understanding is REF_SEL shouldn't matter for this programming. However since SEC_REF is not connected, please disable (like Reg4 = >0x30CF) the input and let me know the result.
    ==>OK, I request to set REG 4=0x30CF

    >>I will check with a co-worker to see if they know more about this case.
    ==>Thank you! My customer would like to solve this issue in this week. So please help me.

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    TI__Mastermind 28530 points

    Hello Sho-san,

    My coworker suggested to try toggling REF_SEL pin for the original setting (Reg 4 = 0x30EF). Then see whether PLL locks well to PRI_REF.

    73,
    Timothy

  • 0 in reply to Timothy T
    Genius 5575 points

    Hi Timothy-san

    Thank you for the reply.
    I understood that we need to toggle REF_SEL pin for the original setting (Reg 4 = 0x30EF). 
    However my customer fixed REF_SEL=Low on the circuit.
    Do we need reset in this case?

    And when we toggle REF_SEL pin? after register setting?

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    Genius 5575 points

    Hi Timothy-san

    Thank you for your support.
    I have one more question.

    You gave me advice that my customer need to toggle REF_SEL pin to improve LOS status.
    Is this operation described in datasheet? If we need to do this operation in this case, I think this is errata.

    Best Regards,
    Sho

  • 0 in reply to Sho Ogane
    TI__Expert 4400 points

    Ogane-san,

    When I had checked on the EVM, this method of toggling RESET or REFSEL works well after register write. But we don't have clear documentation on our end for this issue. Please give us a bit of time to confirm and then we will do the datasheet update.

  • 0 in reply to Madhu Balasubramanian
    Genius 5575 points

    Hi Madhu-san

    Thank you for your support.

    I understood that we should toggle Reset or REF_SEL after resister write when we set 0x30EF.
    Now, we didn't receive the request to add this operation from customer, so we wait your update.

    Best Regards,
    Sho  

  • 0 in reply to Sho Ogane
    TI__Genius 9920 points
    It need time to update datasheet or an application note to show it. If customer need a document to show this method, offline email to Madhu could help you.
  • 0 in reply to Sho Ogane
    TI__Expert 4400 points

    Sho-san,

    We looked in the lab in detail. The REF_SEL pin toggle is not very robust. But the Reset toggle is robust and works all of the time. Lane Boyd will be updating the datasheet and we will let you know once its done.