CDCE913: Requirements for a crystal connected to CDCE913

user5859459

Part Number: CDCE913

When we have measured pulling range of CDCE913, the pulling range was +/-45ppm as a result.
We think it is because the crystal connected the CDCE913 does not satisfy requirements written in "Application Guideline" (SCAA085A).
But some implementors of crystal told us that C1>20fF is very big value and it makes the size of crystal oscillator very big.
We think we should use bigger size of crystal oscillator than now (Abracon: ABM8-27.000MHZ-B2-T, 3.2x2.5mm), but we want it is as small as possible.

What is an important requirement when we search for a crystal oscillator which makes the pulling range wider ?
For example, if you told us "C0/C1 must be less or equal than 220, but C1 does not have to be 20fF", it will be very helpfull for us.

Best Regards

By the way, I have send same question to "Email TI" (www.ti.com/.../webform.tsp) not once or twice, but all of them have rejected.
What was bad ?

over 5 years ago

0 Timothy T over 5 years ago

TI__Mastermind 28530 points

Hello,

Are you measuring pulling on the EVM or your own PCB? Have you done all to reduce stray capacitance?

Have you set register 0x05[7:3] = 0x1f (maximum value of 20 pF), or otherwise minimized external capacitance allowing the varactor to have the the largest value so it may pull frequency while still meeting the requirement of Cload at the target frequency? Having a large varactor diode will help your pull-range. So if you pick a crystal that allows this maximum value of 20 pF with minimum external capacitance, this could help you achieve your goal.

You might also take a look at application note SNAA065A, which talks about designing a vcxo for LMK040xx devices. From this appnote is the recommendation (from section 5.2, Crystal Oscillator Design):
"A reasonable range of values for C0 is single digit picofarads, while C1 will have values that may range from less than 10 femtofarads to greater than 20 femtofarads. Compare these values to nominal values listed on data sheets for some candidate crystals. Also remember to calculate the ratio of C0/C1. In practice, this ratio should be between 200 and 300 for pullable crystals."

user5859459 said:
By the way, I have send same question to "Email TI" (www.ti.com/.../webform.tsp) not once or twice, but all of them have rejected.
What was bad ?

When you say rejected, you received a response? Or a bounced email? I tried submitting a test question and seems to have been accepted. However E2E is the primary support method, so you will want to post your questions to E2E.

73,
Timothy

0 user5859459 over 5 years ago in reply to Timothy T

Prodigy 110 points

> Are you measuring pulling on the EVM or your own PCB?

We have measured it on our own PCB.

> Have you done all to reduce stray capacitance?

We placed CDCE913 and the crystal as close as possible.
(The length of wirings is about 5mm).
But we did not care other things about stray capacitance.

> Have you set register 0x05[7:3] = 0x1f (maximum value of 20 pF),

We measured pulling while setting register 0x05[7:3].
The results is bellow.
0x01 : +/-20ppm
0x04 : +/-44ppm
0x07 : +/-47ppm
0x0a : +/-46ppm
0x0d : +/-45ppm
0x10 : +/-42ppm
0x14 : +/-36ppm

> or otherwise minimized external capacitance allowing the varactor to have the the largest value

We did not place any external capacitance, but we do not know how much stray capacitance is there.

> so it may pull frequency while still meeting the requirement of Cload at the target frequency?

The CL of the crystal on our now PCB is 18pF(typical).
(C0: 7pF(maximum), C1: now inquiring)

> Having a large varactor diode will help your pull-range.
> So if you pick a crystal that allows this maximum value of 20 pF with minimum external capacitance, this could help you achieve your goal.

As I have shown above, the pulling range was not maximized when setting 0x05[7:3]=20pF.
Does it mean that there are some external (stray) capacitance ?

> You might also take a look at application note SNAA065A, which talks about designing a vcxo for LMK040xx devices.
> From this appnote is the recommendation (from section 5.2, Crystal Oscillator Design):
> "A reasonable range of values for C0 is single digit picofarads, while C1 will have values that may range from less than 10 femtofarads to greater than 20 femtofarads.
> Compare these values to nominal values listed on data sheets for some candidate crystals.
> Also remember to calculate the ratio of C0/C1.
> In practice, this ratio should be between 200 and 300 for pullable crystals."

Do you mean that it is applicable for a crystal connected to CDCE913 ?
If so, the required conditions about the crystal is bellow, right?
- "1pF <= C0 <= 9pF" (is better)
- "C1 < 10fF" or "20fF < C1" (is better)
- "200 <= C0/C1 <= 300" (shoude be)

> When you say rejected, you received a response? Or a bounced email?
I have received a message on my web browser.
I do not remember correctly, but I remember that the message mean "please go back on your browser."

> I tried submitting a test question and seems to have been accepted.
> However E2E is the primary support method, so you will want to post your questions to E2E.

OK, I see.

Thank you for your kindly help!
I have asked some additional questions in this post.
Could you please tell me about them?

Best Regards

0 Timothy T over 5 years ago in reply to user5859459

TI__Mastermind 28530 points

Hello,

user5859459 said:
We placed CDCE913 and the crystal as close as possible.
(The length of wirings is about 5mm).
But we did not care other things about stray capacitance.

Best practice is to make a ground cutout in the PCB where the crystal is and the traces to minimize stray capacitance. You can estimate your stray capacitance by determining the capacitance when exactly on frequency vs. what the varactor is adding (or set to 0 and add load capacitance manually). Note CDCE913 adds ~1.5 pF capacitance intrinsically.

user5859459 said:
We measured pulling while setting register 0x05[7:3].
The results is bellow.
0x01 : +/-20ppm
0x04 : +/-44ppm
0x07 : +/-47ppm
0x0a : +/-46ppm
0x0d : +/-45ppm
0x10 : +/-42ppm
0x14 : +/-36ppm

user5859459 said:
The CL of the crystal on our now PCB is 18pF(typical).
(C0: 7pF(maximum), C1: now inquiring)

It may be that the stray capacitance is resulting in total capacitance with the higher values to be so high that the pulling is reduced. Although I'm surprised... you measured -X ppm and +X ppm. I would have expected more lopsided measurements, such as -X ppm and +Y ppm with respect to your target frequency. Perhaps you're measurements were not with respect to target frequency. The crystal should be 0 ppm in error to target frequency at 18 pF load. Varactor capacitance for Vtune from 0 to 1.8 V is 0.3*XCSEL to 1.3*XCSEL; where XCSEL can be from 0 to 20 pF. As you continued to increase the total capacitance, I would have expected lower and lower frequencies.

Note from figure 6 of SCAA085A as capacitance gets higher, the change in ppm becomes smaller. This is probably what you are seeing... and since the varactor goes from 0.3 XCSEL, the minimum capacitance continues to increase. I was thinking XCSEL was just changing the top end.

To your original question of key parameters to look for for best pulling range, lower CL crystal (so 18 pF load crystal is not a best choice) and minimum stray capacitance will lead to the best pull range. Have you seen the pull range simulator in CDCE913 profile of TI Clock Pro? TI Clock Pro is the EVM tool for CDCE913. This may help you determine what you need for best pull range. I think you next step should be to try a crystal with lower CL.

73
Timothy

0 user5859459 over 5 years ago in reply to Timothy T

Prodigy 110 points

Thank you for your detailed information !
I have not used "TI Clock Pro" ever.
I will try it.

I am very sorry for my inaccuracy.
I have measured the pulling range as bellow.
(1) Prepare base clock source (A) and CDCE913's VCXO clock source (B).
(2) Make a cyclic pulse from (A).
(3) Make a cyclic pulse from (B). The number of clocks of the cycle is same as (2).
(4) Observe (2) and (3) by an oscilloscope. The trigger signal is the positive edge of (2).
(5) Measure the phase moving between (3) and (2) in a certain seconds while Vctrl is GND.
(6) Measure it while Vctrl is VDD.
(7) Calculate the delta of maximum/minimum frequency by using the number of clocks of the cycle, its time to observe and the results of (5) and (6).

"XX" in "+/-XXppm" which I wrote meant the half value of (7).
I could not think out other method to observe pulling range in a ppm unit by using our equipments.

Surely, it is shown in figure 6 of SCAA085A that the higher value of CL makes the pulling range narrower.
As you say, it seems better to change a crystal with lower CL value.
Now, I think that the requirements for a crystal is below.
(1) CL : as small as possible (5 ~ 10pF ?) (should be)
(2) C0/C1 ratio : between 200 and 300 (should be)
(3) C1 : less than 10fF or grater than 20fF (is better)
(4) C0 : between 1pF and 9pF (is better)

Could you please confirm whether my understanding is right or not ?
If it is right, I will search for such a crystal.

Best Regards

0 user5859459 over 5 years ago in reply to Timothy T

Prodigy 110 points

Thank you for your introduction of "TI Clock Pro".
I am using "Pulling Range Plot" now.

But I can not understand what some parameters are.
Could you please tell me the meanings of them, and whether my understanding about other parameters is right or not ?
C0 : Shunt Capacitance
C1 : Motional Capacitance
L1 : Motional Inductance
Crystal : ??
CparBoad : ??
CLOAD : Load Capacitance

And also, I can not understand what the value shown above the graph ("Pulling Range XXXX.YYYY").
What is it ?

Best Regards.

0 user5859459 over 5 years ago in reply to Timothy T

Prodigy 110 points

I am sorry for my frequent posts, but a new question came up to us.
Please forgive me.

Why the requirement for C1 is "C1<10fF" or "20fF<C1" ?
We feel a little strangeness about it.
We think that a requirement for a value is usually indicated by only maximum, only minimum or both.
Could you please tell me more detail simply ?

Best Regards

0 Alan O over 5 years ago in reply to user5859459

TI__Mastermind 32575 points

Category	Parameter	Unit	Description
Crystal	C₀	pF	Shunt capacitance
	C₁	fF	Motional capacitance
	L₁	mH	Motional inductance
	C_L	pF	Target load capacitance
PCB	C_Par	pF	Parasitic board capacitance
CDCE9xx	C_Load	pF	Tuning load capacitance inside the device

I think the pulling range value above the graph is computed incorrectly. Instead of relying on this number, you can just visually look at the curve to see the upper and lower ppm values of the plot to determine the total pull range over the Vctrl range.

Alan

0 Alan O over 5 years ago in reply to user5859459

TI__Mastermind 32575 points

I don't think you should be concerned about C1 alone. If you want to design for a target pullability (aka trim sensitivity), you should consider the relationship of all crystal capacitance values as follows:

Pullability (ppm/pF) = C1 * 1e6 / [2 * (C0 + CL)^2 ],
where C0, C1, CL are in pF.

Pullability is a measure of the incremental ppm frequency shift for an incremental change in the value of the load capacitance. It increases with smaller CL and/or smaller C0/C1 ratio.

I recommend you work with crystal vendors to provide a crystal that meets your pullability target, while simultaneously meeting the recommended crystal characteristics in the CDCE913 datasheet.

Alan

0 user5859459 over 5 years ago in reply to Alan O

Prodigy 110 points

I understanded as below.
[Spec of a crystal]
C0 : Shunt Capacitance
C1 : Motional Capacitance
L1 : Motional Inductance
Crystal : Load Capacitance
[Spec of a PCB]
CparBoard : Parasitic Board Capacitance
[Setting of CDCE913]
CLOAD : Load Capacitance set by XCSEL

-The value drawn in right of "Pulling Range" indicates pulling range directly.
But it is less usefull than the value which can be read visually from the curve of the graph.

If there are something wrong, please tell me.

0 user5859459 over 5 years ago in reply to Alan O

Prodigy 110 points

Thanks!
And I am sorry for my late reply.

I applied the formula to the spec of a crystal which have been told us from some vendors.

Crystal-(1)
C0: 0.9 pF
C1: 3.48 fF
CL: 8 pF
Pullability = 0.00348 * 1000000 / [2 * (0.9 + 8)^2]
= 21.97 (ppm/pF)

Crystal (2)
C0: 1.3 pF
C1: 5.08 fF
CL: 8 pF
Pullability = 0.00508 * 1000000 / [2 * (1.3 + 8)^2]
= 29.37 (ppm/pF)

Does this mean that the pulling range of the crystal-(1) is +/-10.99ppm and that of the crystal-(2) is +/14.69ppm ?
I can not understand why a unit of pullability is ppm "/pF".
For example, if we want to achieve +/-100ppm pulling range, should we search for a crystal which has a spec of "Pullability=200 ppm/pF" calculated by the formula ?

Best Regards

0 Alan O over 5 years ago in reply to user5859459

TI__Mastermind 32575 points

Per SCAA085A, the CDCE913's onchip vacator can be tuned through the Vctrl input pin between 0.3x and 1.3x of the center target CL value .

For Crystal 1, the center target CL is 8 pF. The change in the Vctrl is translated in a variation of the varactor value from its center target CL value (8 pF) to the corners of 2.4 pF (0.3 x 8 pF) and 10.4 pF (1.3 x 8 pF) for a total delta of 8 pF. Such a change has the effect to make the output frequency drift, giving a final pulling range of (8 pF × 21.97 ppm/pF) approximately 140 ppm (±70 ppm) over the Vctrl range.

For Crystal 2, the center target CL is 8 pF. Vctrl can change the varactor over the same range as Crystal 1. But the final pulling range will be (8 pF × 29.37 ppm/pF) approximately 235 ppm (±117.5 ppm) over the Vctrl range.

Alan

0 user5859459 over 5 years ago in reply to Alan O

Prodigy 110 points

Thank you for your kindly helps!
All my questions have been resolved.
From now on, I will search for a crystal suitable for the condition.

Best Regards

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CDCE913: Requirements for a crystal connected to CDCE913