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CDCI6214: Has clock hold over function?

Part Number: CDCI6214

Hi

CDCI6214, we design a product (customers need to add new functions to add clock function). We want to ask whether CDCI6214 has clock hold over function, that is, when the input clock is interrupted (or los), the output clock can still be maintained for a period of time, and when the clock restarts, it can glitchless normal work. As a result, I looked at TI's LMK04906/LMK0480X series all have this function. I wonder if CDCI6214 has similar function.

Thank you

Jerry

  • No, CDCI6214 doesn't support holdover. You can also consider LMK05028 and LMK05318 which support standards-compliant (e.g. SyncE, SONET/SDH) holdover capability.

    Alan
  • In reply to Alan O:

    Hi Alan,

    In addition, the specification of CDCI6214 mentions Frequency Increment and Decrement, which increases or decreases the trigger frequency along the rising edges of GPIO1 and 4, but it does not mention the fastest increase in this frequency (or the smallest interval between the two rising edges)? We want to use logic to control the two PINs to dynamically adjust the clock frequency for frequency tracking, so we need to know how fast we can change the frequency in this way.

    Thank you
    Jerry
  • In reply to Jerry Hsueh:

    The frequency increment and decrement pins should not be pulsed faster than 1 MHz, i.e. the minimum delay is 1 us between rising edges on GPIO1/GPIO4.

    What is your end application and use case that requires dynamic clock frequency adjustment?  What data protocol or interface do you intend to use this for, and what are the clock jitter requirements?

    Alan

  • In reply to Alan O:

    Hi Alan,

    Our product is matrix display control board. The original application is shown in the figure (using CDCE937 to control VCO through PWM).

    We intend to use the Frequency Increment and Decrement functions of CDCI6214 to control the clock instead of the original analog way to control VCO to achieve genlock.

    Please help confirm whether CDCI6214 can be implemented.

    Thank you.

    Jerry

  • In reply to Jerry Hsueh:

    What are the video interface (parallel or serial) and data rate?

    What is the video clock jitter requirement?  Clock frequency and signal type (differential or single ended)?

    Do you prefer DCO frequency control via INC/DEC pin control or I2C control?

    Alan

  • In reply to Alan O:

    Hi Alan,

    1. Parallel, data rate from 27Mhz to 165Mhz

    2. Jitter requirement is under 300ps, clock frequency is from 27Mhz to 165Mhz CMOS or LVDS both OK

    3. We prefer DCO frequency control via INC/DEC pin , infact we want to use FPGA to output two pins to control the INC and DEC input.

    Thank you
    Jerry