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LMK03318: Best setting to use for a jitter cleaner audio application

William Plumb
Prodigy 220 points
Part Number: LMK03318

Hi,

I am using the LMK03318 as a jitter cleaner for an Audio clock source that requires a jitter of <5ps. I am converting an MCLK of 24.576MHz to an audio sample clock of 12.288MHz. I have included a plot of the jitter characteristics of the MCLK. Would you be able to recommended the best setting for this application.

Thanks

Regards

Billmclk_jitter_statistics_181201_000.pdf

  • 0
    TI__Genius 16845 points

    Hi Bill,

    The attached file contains the register settings configured for your use case. Use these settings as a starting point if you need to further optimize the configuration.

    Kind regards,
    Lane

  • 0 in reply to Lane Boyd
    Prodigy 220 points
    Hi Lane,

    Thanks for the response. Did you attach a file?

    Regards
    Bill
  • 0 in reply to Lane Boyd
    Prodigy 220 points
    As far as I can tell the file was not attached?
  • 0 in reply to William Plumb
    TI__Genius 16845 points

    Hi Bill,

    My apologies. Please see attached.

    Kind regards,
    Lane

    LMK03328 recommended settings.txt 
    R0	0x0010
R1	0x010B
R2	0x0233
R3	0x0301
R4	0x0401
R5	0x0500
R6	0x0636
R7	0x07DC
R8	0x0822
R9	0x0900
R10	0x0AA8
R11	0x0B02
R12	0x0CD9
R13	0x0D00
R14	0x0E1D
R15	0x0F00
R16	0x1000
R17	0x1100
R18	0x1200
R19	0x1300
R20	0x14FF
R21	0x15FF
R22	0x16FF
R23	0x1703
R24	0x1800
R25	0x19F5
R27	0x1B20
R28	0x1C00
R29	0x1D02
R30	0x1E3B
R31	0x1F30
R32	0x2030
R33	0x21C3
R34	0x2230
R35	0x2330
R36	0x24C3
R37	0x253E
R38	0x26C3
R39	0x2718
R40	0x28C3
R41	0x2918
R42	0x2AC3
R43	0x2B18
R44	0x2CC3
R45	0x2D0F
R46	0x2E00
R49	0x310A
R50	0x3285
R51	0x3303
R52	0x3400
R53	0x3500
R56	0x3802
R57	0x3918
R58	0x3A00
R59	0x3B62
R60	0x3C00
R61	0x3D00
R62	0x3E00
R63	0x3F00
R64	0x4000
R65	0x4101
R66	0x420C
R67	0x4308
R68	0x4401
R69	0x4504
R70	0x4607
R71	0x471F
R72	0x4818
R86	0x5600
R88	0x5800
R89	0x59DE
R90	0x5A01
R91	0x5B18
R92	0x5C01
R93	0x5D4B
R94	0x5E01
R95	0x5F86
R96	0x6001
R97	0x61BE
R98	0x6201
R99	0x63FE
R100	0x6402
R101	0x6547
R102	0x6602
R103	0x679E
R104	0x6800
R105	0x6900
R106	0x6A05
R107	0x6B0F
R108	0x6C0F
R109	0x6D0F
R110	0x6E0F
R115	0x7308
R116	0x7419
R117	0x7500
R118	0x7607
R119	0x7701
R120	0x7800
R121	0x790F
R122	0x7A0F
R123	0x7B0F
R124	0x7C0F
R129	0x8108
R130	0x8219
R132	0x8403
R135	0x8738
R136	0x882B
R137	0x8910
R138	0x8A38
R139	0x8B00
R140	0x8C00
R141	0x8D2B
R142	0x8EFF
R143	0x8F00
R144	0x9000
R145	0x9100
R169	0xA940
R172	0xAC24
R173	0xAD00

  • 0 in reply to Lane Boyd
    Prodigy 220 points

    Hi Lane,

    I have tried these setting and I am not getting anything out of channel 4. I did a register read back after writing the values to the LMK03318. The spreadsheet contains the values written and the values readback.

    I did notice that registers R5, R6, R7, R169, R172 and R173 are loaded with values but these registers are not defined in the datasheet.

    Any ideas on why there is no output?

    Thanks

    Regards

    Bill

    lmk03318_register_setup_181205_000.xlsx

  • 0 in reply to William Plumb
    Prodigy 220 points

    lmk03318_almost_locking_waveform_181205_000.pdfHi Lane,

    I have included a plot of the waveforms. It looks like the output on channel 4 occurs after the VCO calibration cycle but the LMK looses lock shortly afterwards. 

    Yellow: PRIREF_P

    Pink: OUT4_p

    Blue: STATUS0 - PLL VCO Calibration Active (CAL)

    Green: STATUS1 - PLL Loss of Lock (LOL)

    Regards

    Bill

  • 0 in reply to William Plumb
    Prodigy 220 points

    Hi Lane,

    I have been able to get the PLL to lock. To get the PLL to lock I changed how the input clock to PRIREF_P was being generated.

    I would like to use STATUS0 as the output of the PLL clock. I have programmed the following on top of existing values you recommended but do not see any output from STATUS0. Would you be able to advise on setting STATUS0 as the output of the PLL clock?

    Regards

    Bill

    0x1E=0x3B // R30

    0x2D=0x18  // R45 Set STATUS0 as a clock output with /4

    0x2E= 0x61 // R46 Set STATUS0 integer divide value 98 (4816896000/(4*98)=12.288MHz

    lmk03318_locking_waveform_181210_000.pdf

    4816896000
  • 0 in reply to Lane Boyd
    Prodigy 220 points
    Hi Lane,

    I have been able to get the PLL to lock. To get the PLL to lock I changed how the input clock to PRIREF_P was being generated.

    I would like to use STATUS0 as the output of the PLL clock. I have programmed the following on top of existing values you recommended but do not see any output from STATUS0. Would you be able to advise on setting STATUS0 as the output of the PLL clock?

    Regards

    Bill

    0x1E=0x3B // R30

    0x2D=0x18 // R45 Set STATUS0 as a clock output with /4

    0x2E= 0x61 // R46 Set STATUS0 integer divide value 98 (4816896000/(4*98)=12.288MHz
  • 0 in reply to William Plumb
    TI__Genius 16845 points
    Hi Bill,

    I set 0x2D = 0x1C to disable STATUS1 and enable the STATUS0 CMOS clock

    Kind regards,
    Lane
  • 0 in reply to Lane Boyd
    Prodigy 220 points

    Hi Lane,

    I have tried both 0x2D=0x1C and 0x2D=0x18. Both setting should result in a clock signal out of STATUS0. Neither one is working with my setup. I have included a complete list of my register writes and also the readback values.

    Any ideas on why there would be no output from STATUS0?

    Regards

    Bill

    register_writes_181211_000.xlsx

  • 0 in reply to Lane Boyd
    Prodigy 220 points
    Hi Lane,

    I have tried both 0x2D=0x1C and 0x2D=0x18. Both setting should result in a clock signal out of STATUS0. Neither one is working with my setup. I have included a complete list of my register writes and also the readback values.

    Any ideas on why there would be no output from STATUS0?

    Regards

    Bill
  • 0 in reply to William Plumb
    TI__Genius 9920 points

    Hi Bill,

    I converted your register setting into TICs Pro configuration. Didn't find any problem.

    Could you use reset bit (R12.bit 7) again to see what happened?

    LMK03318 TICS Pro configuration.zip

    Best Regards,

    Shawn

  • 0 in reply to Shawn Han
    TI__Genius 16845 points
    Hi Bill,

    Sorry for the delay. As Shawn mentioned, you may need to toggle the reset bit in order to re-calibrate the PLL if the outputs are not present.

    One thing that may help with your debug is setting the STATUS1 output to PLL LOL in order to determine whether the PLL is locked.

    Kind regards,
    Lane