Other Parts Discussed in Thread: ADS54J60EVM,
Hello TI experts,
I have a question which I tried to solve in the thread:
...and it turned out that the problem was that on the eval board of TI the ADC sample clock disappears when the ADLY is set to 950 ps and when "ADLY Input" is set to "Divider". However when we set "ADLY Input" to "Divider + DCC" then the ADLY is not affecting the output signal
The datasheet is not very explicit on the "DCLKoutX_ADLY_MUX". It states on page 57: "This register selects the input to the analog delay for the device clock. Used when DCLKoutX_MUX = 3." on the other hand on page 35 in the diagram it looks like DCC is after the ADLY stage.
Now my question: Why does this bit influence the output signal when only the ADLY is changed?
Regards
Goran