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LMK04828: Why does the DCC influence the output signal when driving the ADLY

Part Number: LMK04828

Hello TI experts,

I have a question which I tried to solve in the thread:

...and it turned out that the problem was that on the eval board of TI the ADC sample clock disappears when the ADLY is set to 950 ps and when "ADLY Input" is set to "Divider". However when we set "ADLY Input" to "Divider + DCC" then the ADLY is not affecting the output signal
The datasheet is not very explicit on the "DCLKoutX_ADLY_MUX". It states on page 57: "This register selects the input to the analog delay for the device clock. Used when DCLKoutX_MUX = 3." on the other hand on page 35 in the diagram it looks like DCC is after the ADLY stage.

Now my question: Why does this bit influence the output signal when only the ADLY is changed?

Regards

Goran

  • Hi Goran,

    I have assigned a responsible engineer to your post. He will get back to you soon.

    Kind regards,
    Lane

  • Hello Goran,

    What is the frequency of the output for which you are changing device clock ADLY? Please note as per electrical table specs in datasheet ADLY is only rated to 1536 MHz. It's been my experience that maybe a few stages of analog delay will work for higher frequencies, but the signal is too fast and it dies in the delay chain resulting in no output at higher ADLY setting.

    Also note, when using ADLY on device clock your noise floor will increase.

    73,
    Timothy
  • In reply to Timothy T:

    Hello Timothy,

    The output frequency needed for the TI eval board ADS54J60EVM is 1 GHz. I guess the fADLYmax (Maximum analog delay frequency) is referred to the line after the divider, as shown in block diagram page 34 figure 12. By the way, maybe you can explain to us engineers how you set "DCLKoutX_MUX = 4" if you have only 2 bits :-) as indicated in the datasheet on page 19. I guess this is a typo.
    However, if you need my complete setup (register configuration) please get it from my initial post. There you will find my we have to do these setup and the complete register configuration as well... maybe this is as well the easiest way for you TI support guys to reproduce the problem with your own TI hardware and software.

    Cheers
    Goran
  • In reply to Goran Marinkovic:

    Hello Goran,

    You are correct about the figure 13. The DCC and Analog delay are swapped. The DCC block to be consistent should also be labeled HS/DCC, for half step & duty cycle correction.
    Please refer to Figure 12 which gives the detailed flow of the output channel. The be consistent on ordering an mux values, Figure 12 should have the top input connect to before HS/DCC and the bottom after HS/DCC.

    About the control of this feature, referring to figure 12. You can see the DCLKoutX_MUX (2 bits) selects from one of four sources. The forth being the analog delay path. When using this forth analog delay path, there is a second control DCLKoutX_ADLY_MUX which selects the HS/DCC mode. On page 19, it is clarifying the mode of operation being analog delay. However the typo may be the omission of the DCLKoutX_ADLY_MUX = 1.

    As for the ADS54J60EVM, I think the ADLY input (DCLKoutX_ADLY_MUX) on the LMK04828 : SYSREF and SYNC tab should have been placed next to DCLK source (DCLKoutX_MUX) on the LMK04828 : Clock Outputs tab.

    Having set the DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1, you should find the ADLY output works for the full range? I was able to confirm that without enabling HS/DCC (DCLKoutX_ADLY_MUX = 1), I noticed the same issue you had.

    73,
    Timothy
  • In reply to Timothy T:

    >"You are correct about the figure 13. The DCC and Analog delay are swapped. The DCC block to be consistent should also be labeled HS/DCC, for half step & duty cycle correction. Please refer to Figure 12 which gives the detailed flow of the output channel."
    Fine.

    > "The be consistent on ordering an mux values, Figure 12 should have the top input connect to before HS/DCC and the bottom after HS/DCC."
    I think the drawing is ok since you may define the lower input on the MUX to be DCLKoutX_ADLY_MUX = 0 and the upper to be DCLKoutX_ADLY_MUX = 1. And the drawing is more clear if there are less crossing of wires.

    >"About the control of this feature, referring to figure 12. You can see the DCLKoutX_MUX (2 bits) selects from one of four sources. The forth being the analog delay path. When using this forth analog delay path, there is a second control DCLKoutX_ADLY_MUX which selects the HS/DCC mode. On page 19, it is clarifying the mode of operation being analog delay. However the typo may be the omission of the DCLKoutX_ADLY_MUX = 1."
    Sure, it is a tpyo. Since the path should be DCLKoutX_MUX = 3. According to the datasheet DCLKoutX_ADLY_MUX makes only sense if DCLKoutX_MUX = 3. Which is consistent with my reports. The following makes never sense: DCLKoutX_MUX = 4! Hence please correct your datasheet for example as follows: DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1. This works (except the reported settings causing the reported problems)

    "As for the ADS54J60EVM, I think the ADLY input (DCLKoutX_ADLY_MUX) on the LMK04828 : SYSREF and SYNC tab should have been placed next to DCLK source (DCLKoutX_MUX) on the LMK04828 : Clock Outputs tab."
    "Having set the DCLKoutX_MUX = 3 and DCLKoutX_ADLY_MUX = 1, you should find the ADLY output works for the full range?"
    Yes, this is what we do, and yes it works as we confirmed by measurement and documented in the logs before.

    "I was able to confirm that without enabling HS/DCC (DCLKoutX_ADLY_MUX = 1), I noticed the same issue you had."
    What are the next steps? Whatever you do, let me guess it will take some time. Hence, please keep me posted when your experts find out why this happens... I try to understand the problem rather than having to rely on a empiric finding.

    Cheers... or as well 73 to you
    Goran