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CDCM7005: SETUP

Michelle Tange
Prodigy 120 points
Part Number: CDCM7005
Other Parts Discussed in Thread: ADC16DV160,

HI

I want to connect both a DAC (DAC5682) and an ADC (ADC16DV160) to an FPGA board (NEXYS VIDEO) via an FMC connector. I have a very limited amount of pins, so I have decided to use the CDCM7005 to generate the various clock signals from 1 signal. I have gone through the datasheet but there are Things i am not sure about.

I want to use the CDCM7005 to generate a 320 MHz and a 160 MHz clock signal.

One option is to send 1 clock signal at 320 MHz from the FPGA.
Another option is to generate the 320 MHz clock signal from a VCXO.
In both cases I also generate a clock signal to go back to the FPGA for synchronisation with the DAC and ADC.

Im an not set on the frequency, I might want to sample slower.

My question regards the reference clock (PRI_REF, SEC_REF)
If i look at the example in the datasheet 10.1.1 it seems like the reference clock is 128 times smaller than the input clock, is that a general factor or how is the value 3.84 MHz determined?

Another question is wether the reference clock is nessassary or not.
Do I only need the reference clock if I use the PLL-mode? Do I need it if the 320 MHz clock is generated from the VCXO, or do I need it in general?

Regards
Michelle

 

  • 0
    TI__Genius 16845 points
    Hi Michelle,

    To answer your first question, the input frequency can be any frequency that can divide to a common phase detector frequency (PFD). In other words, F_ref / M = F_VCXO / (P * N) = PFD.
    For CDCM7005: F_CPmax = 100MHz; M_max = 2^10; N_max = 2^12 ; P_max =16 . For the datasheet Figure 24, this could correspond to a PFD of 3.84MHz. Lower phase detector frequencies allows for higher loop bandwidth and smaller external loop filter capacitor C2 value.

    To answer your second question, the reference clock must be used in PLL-mode. If you generate the 320MHz clock from the VCXO without using the reference clock, the output will be locked to the VCXO rather than to the reference input. The VCXO will have some frequency tolerance and output frequency depending on the control voltage, so the output frequency may vary from part to part.

    I hope this information helps

    Kind regards,
    Lane