LMK04828: Resetting the divider and generating sysref

Hello Izik,

I understand you are distributing a 3 GHz signal through CLKin1/Fin pins to DAC with SYSREF, but also want to divide /30 to generate 100 MHz which has a known phase as defined by an external SYNC.  I'm not sure your SYSREF frequency, but that wouldn't expect it to impact my answer.

This is possible.  To achieve this you will need to send a SYNC pulse into the CLKin0 input and meet timing to CLKin1 input at 3 GHz.  The period of 3 GHz is is ~333 ps.  I recommend the SYNC pulse to occur on falling edge of 3 GHz input clock to CLKin1.  See attached document for example plots.

Using LMK04828 as JESD204B Fan-out, 3 GHz setup and hold.pdf

When giving this SYNC, configure the device such that CLKin0_OUT_MUX = 0 (Drive SYSREF_MUX), SYSREF_MUX = 0 (Normal SYNC), SYSREF_CLKin0_MUX = 0 (SYSREF_MUX).  Now for each divider you want to reset to have deterministic phase, set SYNC_DISX = 0.  Also to ensure SYSREF signal is synchronized, set SYNC_DISSYSREF = 0.  This allows your external SYNC pulse on CLKin0 to reset the dividers.  After the SYNC pulse is given, set all SYNC_DISX/SYSREF bits = 1 so that your SYSREF pulse does't disrupt the output.  Please refer to section 9.3.2 for more details on configuring SYSREF... as SYNC and SYSREF share the same clock path.  Depending on your SYSREF configuration, you will need to re-configure the muxes.

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To achieve timing of SYSREF to DACCLK at DAC input.  I recommend adjusting the digital delay on the SYSREF.  This means keeping device clock fixed and adjusting SYSREF clock.  While the device clock path has 25 ps steps of analog delay, it will increase your noise floor.  While you can do this to get finer timing adjustments, analog delay also has increased variation over PVT vs. digital delay, so depending on DAC frequency, you may need to accommodate for shift over temp.  Note, you could also use the 150 ps step analog delay step in sysref path and the digital delay step in sysref path together such that the difference is 166.5 ps - 150 ps = 16.5 ps.  This gives an effective time adjustment of ~16.5 ps.  It will actually very as the analog delay steps are not perfectly 150 ps.  Also, as above, there will be analog delay sensitivities with respect to PVT you may need to accommodate for.  Normally digital delay is sufficient to meet setup and hold times.

73,
Timothy

Hello Izik,

If I could come up with a solution, I think I need more info.

Is your SYSREF 100 MHz?

Do you have multiple LMK04828 you want synchronized together from an asynchronous request?

Do want the LMK04828 SYSREF aligned  with some other low frequency associated with your asynchronous request?
      * If so can you advise what frequency it is?  That is the lowest frequency to which you need determinism and a slip of one cycle is transparent?  Perhaps the SYSREF frequency?

Note from JESD204B requirements.  JESD204B does not care if when you issue the SYSREF pulse provided time_of_SYSREF modulus Local_Multi_Frame_Clock_period = 0.  Your application may (or may not) care if this time is the same.  JESD204B has deterministic timing only within the LMFC period.  Beyond that you must keep track of things.

By definition, the SYSREF period is equal to some integer multiple of LMFC period.  Therefore SYSREF_period modulus Local_Multi_Frame_Clock_period = 0.

Izik said:

It means that for example, if the div. reset occurs 200 nS after the rise of the sync, it has to be the same constant number between repeated sync events and also remain 200nS between power-up cycles.

It would, provided the input conditions are met... except by definition of the asynchronous SYNC request, the time will not be strictly the same.  In an ideal/theoretical system the timing will vary from 0 seconds to just less than 1 DACCLK period due to asynchronous nature of your input.  Is uncertainty of SYNC to SYSREF of +/- 1 (or 0 to 2 cycles) that much worse for your system?

73,
Timothy