This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
LMK04133 / Clock Design Tool
Part Number: LMK04131
I have a question regarding the clock inputs to the lmk04131.
I do not know how to choose the values of the VCXO connected to the OSCin and the VCO connected to the reference clock CLKin0/1
I need 160 MHz and 320 MHz output. I would like to know how to determine the input frequencies.
To design your own Clock Tree solution, visit WEBENCH Clock ArchitectMore information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Timothy T:
The pdf is great, thank you so much.
just a remark; the lmk04131 was recomented to by in another post, based on my application. I am just not sure how to set it up.
My problem is that I am running a DAC and an ADC from an FPGA through a low pin Count FMC, so I have a very limited amount of clock pins available. I have 3 differential pairs but it would be beneficial for my design only to use 2. I need 1 for syncronizing the data coming back from the ADC and 1 coming from the lmk04131 to sycronize the data going to the DAC.
As mentioned I do have a 3rd one to use as reference clock to the lmk04131 but I would really like to use that FMC pin for data transfer.
If I bypass the first PLL as you mention does that mean I don't need a reference clock, just the external VCXO for the second PLL or do I need a reference clock no matter what?
I tryed the clock architect simulation and apparently I cant use the lmk04131 but with the lmk04133 it Works. It suggests the internal VCO to 1920MHz and a reference input of 19.2MHz. But that does not divide into an even number with the 160 and 320 MHz signals. It does not say anything about the value of the external VCXO eather.
I do not understand your first remark. Do I only need a jitter cleaner device if the reference signal comes directly from the FPGA? If I look at the datasheet for the lmk04133 the system diagram looks like this
Here the reference clock is generated from a VCO. Is that the one that should be divided into an nice even number?
In reply to Michelle Tange:
To design your own Clock Tree solution, visit WEBENCH Clock Architect !
More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.