Other Parts Discussed in Thread: LMK05028, LMK05318
hello
in a previous post, I had asked if the LMK04826 can be used in a system with a varying duty cycle signal at its CLKIN inputs. Anyhow the response was that the LMK looks at the rising edges so it should work with our CLK input.
Anyhow I would like to attach a pdf that shows the clock signal that we are using but your forum doesnt permit it. Is there a way for me to provide you a waveform? For now you can think of a waveform where its HIGH for 3 system clock cycles, then OFF for 1 system clock cycle and then ON for one system clock and then OFF for one system clock cycle and then it finally repeats itself. its 1 WIDE PULSE followed by 1 narrow pulse before repeating itself.
Right now the LMK indicates that PLL1 is NOT LOCKED. However after using the status pins to output the INTERNAL DIVIDERS, we can clearly see that the dividers are working correctly and furthermore, the divided frequency into the PLL1 IS CORRECT.
Can anyone explain to us why the LMK reports that PLL1 is not locked but internal circuitry seems to be OK? We even increased the LOCK window size and still NO LOCK. We can only guess that this part does not like clk inputs that do not have 50 % duty cycle which is different from what we were initally told.
Is this the problem or should we be looking elsewhere??
Please assist.
Thanks
