CDCVF2505: Setting for delay time

Hi Ishiwata,

1, It is impossible for 100 MHz. Fig. 10 shows a example for 100 MHz.
100MHz period is 10 ns. From datasheet "7.7 Switching Characteristics", we know tr/tf max can reach 2 ns under "CL = 25 pF, VDD = 3.3 V ±0.3 V
". We can think of the Yx clock waveform had become a triangle-like waveform. So 25 pF load is the max limit for the 100 MHz application.

2, Lower frequency would get more opportunity to delay longer with a litter bigger capacitance on Yn, not more on CLKOUT.

3, Besides Yx delay, we also can consider CLKin delay with cap load. But it would degrade jitter performance.

4, TI would not guarantee the usage over spec.

Hope you can find a trade off method to get 2ns delay for your applications.

Best Regards,
Shawn