Hello Team,
we are facing some challenges during the SPI communication with the device.
Things are looking now working, but out of the datasheet there are gray area:
in our first attempt we implemented the SPI write as it is shown in figure 32 on page 30 of the data sheet. There were the following differences:
- SCL starts at low value to have the same conditions before and after transfer, so the first transition of SCLK was a rising edge 425ns after the falling edge of SCSn
- write data was supplied via SDI instead of SDO
This seemed to work, but later on we found out that it was not reliable. According to section 8.5.1.1 the chip operates on the rising edge of SCL, but the timing t6 in table 9 suggests that the chip operates on both edges (by the way: I would expect a max delay specification for t6 instead of a min delay). As it is not allowed to toggle SCL while SCS is high, my conclusion was that the falling edge of SCL has to be applied before SCS is released and that timing t8 also applies for the falling edge of SCL.
So the new implementation switches the SCL to low first and de-asserts SCS later. With this new implementation there are no issues so far.
Can you please review and let us know if you have suggestions for further improvements?
Thanks,
SunSet
