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LMX2594: A few questions and comments on the LMX2594

Intellectual 2870 points

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Part Number: LMX2594

Comments are in reference to the LMX2594 datasheet identified as "SNAS696A –MARCH 2017–REVISED AUGUST 2017"

Table 2 refers to FRAC_ORDER but this field doesn't appear in the register map.  Is this value set up by field MASH_ORDER in register R44?

Side note, MASH is not defined in the datasheet.  Is this acronym readily known to RF engineers?

Section 7.5.1, step 4, refers to programming all registers.  Is it necessary to write registers that have no user-programmable fields?  What about registers whose reset default values are already acceptable?

Finally, I wanted to let you know about a few issues in Figure 37 and Table 26 that should be fixed next time you rev the datasheet.  No help needed as the answers are already shown in Table 22.

  • VCO_DACISET in Figure 37 is implied not to include bit [0], although Table 22 and Table 26 make it clear that it does.
  • R17[13:11] are shown as a single bit
  • R19[13:11] are shown as a single bit and could be misleading if the user doesn't check against Table 22 because these bits are shown with different values in Table 22.
  • VCO_SEL_STRT_EN is absent from Table 26.


David C

  • David,

    Thank you for the feedback, we will update our datasheet with this:

    1. MASH_ORDER and FRAC_ORDER are the same. MASH stands for (M)ulti st(A)ge noise (SH)aping. This means that there are several stages.

    2. Registers R0 to R78 all need to be programmed. In general, you have to assume that any register that shows 1's and 0's only that these DO have to be programmed and are NOT the power on reset state. Now some of the higher registers don't need programming for example:
    a. Readback only registers don't need to be programmed R107 - R112
    b. Register relating to settins for RAMPING do not neeed to be programmed if RAMP_EN=0 (R79-R106)

    3. Thanks for the datasheet feedback, we will clean this up.